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[src/trunk]: src/sys/arch/arm/broadcom Be consistent and use #define<space>
details: https://anonhg.NetBSD.org/src/rev/148a6b90c216
branches: trunk
changeset: 328084:148a6b90c216
user: matt <matt%NetBSD.org@localhost>
date: Wed Mar 26 02:39:57 2014 +0000
description:
Be consistent and use #define<space>
diffstat:
sys/arch/arm/broadcom/bcm53xx_reg.h | 888 ++++++++++++++++++------------------
1 files changed, 444 insertions(+), 444 deletions(-)
diffs (truncated from 1169 to 300 lines):
diff -r 60d8a8d4977e -r 148a6b90c216 sys/arch/arm/broadcom/bcm53xx_reg.h
--- a/sys/arch/arm/broadcom/bcm53xx_reg.h Wed Mar 26 01:14:52 2014 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_reg.h Wed Mar 26 02:39:57 2014 +0000
@@ -45,183 +45,183 @@
* 0xffff_0000..0xffff_043f 1088B Internal SKU ROM Region
* 0xffff_1000..0xffff_1fff 4KB Enumeration ROM Register Region
*/
-#define BCM53XX_PCIE0_OWIN_PBASE 0x08000000
-#define BCM53XX_PCIE0_OWIN_SIZE 0x04000000
-#define BCM53XX_PCIE0_OWIN_MAX 0x08000000
+#define BCM53XX_PCIE0_OWIN_PBASE 0x08000000
+#define BCM53XX_PCIE0_OWIN_SIZE 0x04000000
+#define BCM53XX_PCIE0_OWIN_MAX 0x08000000
-#define BCM53XX_IOREG_PBASE 0x18000000
-#define BCM53XX_IOREG_SIZE 0x00200000
+#define BCM53XX_IOREG_PBASE 0x18000000
+#define BCM53XX_IOREG_SIZE 0x00200000
-#define BCM53XX_ARMCORE_PBASE 0x19000000
-#define BCM53XX_ARMCORE_SIZE 0x00100000
+#define BCM53XX_ARMCORE_PBASE 0x19000000
+#define BCM53XX_ARMCORE_SIZE 0x00100000
-#define BCM53XX_NAND_PBASE 0x1c000000
-#define BCM53XX_NAND_SIZE 0x01000000
+#define BCM53XX_NAND_PBASE 0x1c000000
+#define BCM53XX_NAND_SIZE 0x01000000
-#define BCM53XX_SPIFLASH_PBASE 0x1d000000
-#define BCM53XX_SPIFLASH_SIZE 0x01000000
+#define BCM53XX_SPIFLASH_PBASE 0x1d000000
+#define BCM53XX_SPIFLASH_SIZE 0x01000000
-#define BCM53XX_PCIE1_OWIN_PBASE 0x40000000
-#define BCM53XX_PCIE1_OWIN_SIZE 0x04000000
-#define BCM53XX_PCIE1_OWIN_MAX 0x08000000
+#define BCM53XX_PCIE1_OWIN_PBASE 0x40000000
+#define BCM53XX_PCIE1_OWIN_SIZE 0x04000000
+#define BCM53XX_PCIE1_OWIN_MAX 0x08000000
-#define BCM53XX_PCIE2_OWIN_PBASE 0x48000000
-#define BCM53XX_PCIE2_OWIN_SIZE 0x04000000
-#define BCM53XX_PCIE2_OWIN_MAX 0x08000000
+#define BCM53XX_PCIE2_OWIN_PBASE 0x48000000
+#define BCM53XX_PCIE2_OWIN_SIZE 0x04000000
+#define BCM53XX_PCIE2_OWIN_MAX 0x08000000
-#define BCM53XX_IO_SIZE (BCM53XX_IOREG_SIZE \
+#define BCM53XX_IO_SIZE (BCM53XX_IOREG_SIZE \
+ BCM53XX_ARMCORE_SIZE \
+ BCM53XX_PCIE0_OWIN_SIZE \
+ BCM53XX_PCIE1_OWIN_SIZE \
+ BCM53XX_PCIE2_OWIN_SIZE)
-#define BCM53XX_REF_CLK (25*1000*1000)
+#define BCM53XX_REF_CLK (25*1000*1000)
-#define CCA_UART_FREQ BCM53XX_REF_CLK
+#define CCA_UART_FREQ BCM53XX_REF_CLK
/* Chip Common A */
-#define CCA_MISC_BASE 0x000000
-#define CCA_MISC_SIZE 0x001000
-#define CCA_UART0_BASE 0x000300
-#define CCA_UART1_BASE 0x000400
+#define CCA_MISC_BASE 0x000000
+#define CCA_MISC_SIZE 0x001000
+#define CCA_UART0_BASE 0x000300
+#define CCA_UART1_BASE 0x000400
/* Chip Common B */
-#define CCB_BASE 0x000000
-#define CCB_SIZE 0x030000
-#define PWM_BASE 0x002000
-#define MII_BASE 0x003000
-#define RNG_BASE 0x004000
-#define TIMER0_BASE 0x005000
-#define TIMER1_BASE 0x006000
-#define SRAB_BASE 0x007000
+#define CCB_BASE 0x000000
+#define CCB_SIZE 0x030000
+#define PWM_BASE 0x002000
+#define MII_BASE 0x003000
+#define RNG_BASE 0x004000
+#define TIMER0_BASE 0x005000
+#define TIMER1_BASE 0x006000
+#define SRAB_BASE 0x007000
-#define CRU_BASE 0x00b000
-#define DMU_BASE 0x00c000
+#define CRU_BASE 0x00b000
+#define DMU_BASE 0x00c000
-#define DDR_BASE 0x010000
+#define DDR_BASE 0x010000
-#define PCIE0_BASE 0x012000
-#define PCIE1_BASE 0x013000
+#define PCIE0_BASE 0x012000
+#define PCIE1_BASE 0x013000
#ifdef BCM5301X
-#define UART2_BASE 0x008000
-#define SMBUS1_BASE 0x009000
-#define PCIE2_BASE 0x014000
+#define UART2_BASE 0x008000
+#define SMBUS1_BASE 0x009000
+#define PCIE2_BASE 0x014000
#define SDIO_BASE 0x020000
-#define EHCI_BASE 0x021000
-#define OHCI_BASE 0x022000
-#define GMAC0_BASE 0x024000
-#define GMAC1_BASE 0x025000
-#define GMAC2_BASE 0x026000
-#define GMAC3_BASE 0x027000
-#define NAND_BASE 0x028000
+#define EHCI_BASE 0x021000
+#define OHCI_BASE 0x022000
+#define GMAC0_BASE 0x024000
+#define GMAC1_BASE 0x025000
+#define GMAC2_BASE 0x026000
+#define GMAC3_BASE 0x027000
+#define NAND_BASE 0x028000
#define QSPI_BASE 0x029000
#define I2S_BASE 0x02A000
#define DMAC_BASE 0x02C000
#endif
#ifdef BCM563XX
-#define UART2_BASE 0x007000
-#define SMBUS1_BASE 0x008000
-#define WDT_BASE 0x009000
-#define PKA_BASE 0x00a000
-#define SMBUS2_BASE 0x00b000
+#define UART2_BASE 0x007000
+#define SMBUS1_BASE 0x008000
+#define WDT_BASE 0x009000
+#define PKA_BASE 0x00a000
+#define SMBUS2_BASE 0x00b000
#define DMAC_BASE 0x020000
-#define GMAC0_BASE 0x022000
-#define GMAC1_BASE 0x023000
-#define NAND_BASE 0x026000
-#define QSPI_BASE 0x027000
-#define EHCI_BASE 0x02A000
-#define OHCI_BASE 0x02B000
+#define GMAC0_BASE 0x022000
+#define GMAC1_BASE 0x023000
+#define NAND_BASE 0x026000
+#define QSPI_BASE 0x027000
+#define EHCI_BASE 0x02A000
+#define OHCI_BASE 0x02B000
#endif
-#define IDM_BASE 0x100000
-#define IDM_SIZE 0x100000
+#define IDM_BASE 0x100000
+#define IDM_SIZE 0x100000
/* Chip Common A */
#ifdef CCA_PRIVATE
-#define MISC_CHIPID 0x000
-#define CHIPID_REV __BITS(19,16)
-#define CHIPID_ID __BITS(15,0)
-#define ID_BCM53010 0xcf12 // 53010
-#define ID_BCM53011 0xcf13 // 53011
-#define ID_BCM53012 0xcf14 // 53012
-#define ID_BCM53013 0xcf15 // 53013
-#define ID_BCM56340 0xdc14 // 56340
+#define MISC_CHIPID 0x000
+#define CHIPID_REV __BITS(19,16)
+#define CHIPID_ID __BITS(15,0)
+#define ID_BCM53010 0xcf12 // 53010
+#define ID_BCM53011 0xcf13 // 53011
+#define ID_BCM53012 0xcf14 // 53012
+#define ID_BCM53013 0xcf15 // 53013
+#define ID_BCM56340 0xdc14 // 56340
-#define MISC_CAPABILITY 0x004
-#define CAPABILITY_JTAG_PRESENT __BIT(22)
-#define CAPABILITY_UART_CLKSEL __BITS(4,3)
-#define UART_CLKSEL_REFCLK 0
-#define UART_CLKSEL_INTCLK 1
+#define MISC_CAPABILITY 0x004
+#define CAPABILITY_JTAG_PRESENT __BIT(22)
+#define CAPABILITY_UART_CLKSEL __BITS(4,3)
+#define UART_CLKSEL_REFCLK 0
+#define UART_CLKSEL_INTCLK 1
/* 2 & 3 are reserved */
-#define CAPABILITY_BIG_ENDIAN __BIT(2)
-#define CAPABILITY_UART_COUNT __BITS(1,0)
+#define CAPABILITY_BIG_ENDIAN __BIT(2)
+#define CAPABILITY_UART_COUNT __BITS(1,0)
-#define MISC_CORECTL 0x008
-#define CORECTL_UART_CLK_EN __BIT(3)
-#define CORECTL_GPIO_ASYNC_INT_EN __BIT(2)
-#define CORECTL_UART_CLK_OVERRIDE __BIT(0)
+#define MISC_CORECTL 0x008
+#define CORECTL_UART_CLK_EN __BIT(3)
+#define CORECTL_GPIO_ASYNC_INT_EN __BIT(2)
+#define CORECTL_UART_CLK_OVERRIDE __BIT(0)
-#define MISC_INTSTATUS 0x020
-#define INTSTATUS_WDRESET __BIT(31) // WO2C
-#define INTSTATUS_UARTINT __BIT(6) // RO
-#define INTSTATUS_GPIOINT __BIT(0) // RO
+#define MISC_INTSTATUS 0x020
+#define INTSTATUS_WDRESET __BIT(31) // WO2C
+#define INTSTATUS_UARTINT __BIT(6) // RO
+#define INTSTATUS_GPIOINT __BIT(0) // RO
-#define MISC_INTMASK 0x024
-#define INTMASK_UARTINT __BIT(6) // 1 = enabled
-#define INTMASK_GPIOINT __BIT(0) // 1 = enabled
+#define MISC_INTMASK 0x024
+#define INTMASK_UARTINT __BIT(6) // 1 = enabled
+#define INTMASK_GPIOINT __BIT(0) // 1 = enabled
/* Only bits [23:0] are used in the GPIO registers */
-#define GPIO_INPUT 0x060 // RO
-#define GPIO_OUT 0x064
-#define GPIO_OUTEN 0x068
-#define GPIO_INTPOLARITY 0x070 // 1 = active low
-#define GPIO_INTMASK 0x074 // 1 = enabled (level)
-#define GPIO_EVENT 0x078 // W1C, 1 = edge seen
-#define GPIO_EVENT_INTMASK 0x07c // 1 = enabled (edge)
-#define GPIO_EVENT_INTPOLARITY 0x084 // 1 = falling
-#define GPIO_TIMER_VAL 0x088
-#define TIMERVAL_ONCOUNT __BITS(31,16)
-#define TIMERVAL_OFFCOUNT __BITS(15,0)
+#define GPIO_INPUT 0x060 // RO
+#define GPIO_OUT 0x064
+#define GPIO_OUTEN 0x068
+#define GPIO_INTPOLARITY 0x070 // 1 = active low
+#define GPIO_INTMASK 0x074 // 1 = enabled (level)
+#define GPIO_EVENT 0x078 // W1C, 1 = edge seen
+#define GPIO_EVENT_INTMASK 0x07c // 1 = enabled (edge)
+#define GPIO_EVENT_INTPOLARITY 0x084 // 1 = falling
+#define GPIO_TIMER_VAL 0x088
+#define TIMERVAL_ONCOUNT __BITS(31,16)
+#define TIMERVAL_OFFCOUNT __BITS(15,0)
#define GPIO_TIMER_OUTMASK 0x08c
#define GPIO_DEBUG_SEL 0x0a8
-#define MISC_WATCHDOG 0x080 // 0 disables, 1 resets
+#define MISC_WATCHDOG 0x080 // 0 disables, 1 resets
-#define MISC_CLKDIV 0x0a4
-#define CLKDIV_JTAG_MASTER_CLKDIV __BITS(13,9)
-#define CLKDIV_UART_CLKDIV __BITS(7,1)
+#define MISC_CLKDIV 0x0a4
+#define CLKDIV_JTAG_MASTER_CLKDIV __BITS(13,9)
+#define CLKDIV_UART_CLKDIV __BITS(7,1)
-#define MISC_CAPABILITY2 0x0ac
+#define MISC_CAPABILITY2 0x0ac
#define CAPABILITY2_GSIO_PRESENT __BIT(1) // SPI exists
-#define MISC_GSIOCTL 0x0e4
-#define GSIOCTL_STARTBUSY __BIT(31)
-#define GSIOCTL_GSIOMODE __BIT(30) // 0 = SPI
-#define GSIOCTL_ERROR __BIT(23)
-#define GSIOCTL_BIGENDIAN __BIT(22)
-#define GSIOCTL_GSIOGO __BIT(21)
-#define GSIOCTL_NUM_DATABYTES __BITS(17,16) // actual is + 1
-#define GSIOCTL_NUM_WAITCYCLES __BITS(15,14) // actual is + 1
-#define GSIOCTL_NUM_ADDRESSBYTES __BITS(13,12) // actual is + 1
-#define GSIOCTL_GSIOCODE __BITS(10,8)
-#define GSIOCODE_OP_RD1DATA 0
-#define GSIOCODE_OP_WRADDR_RDADDR 1
-#define GSIOCODE_OP_WRADDR_XFRDATA 2
-#define GSIOCODE_OP_WRADDR_WAIT_XFRDATA 3
-#define GSIOCODE_XFRDATA 4
-#define GSIOCTL_GSIOOP __BITS(7,0)
+#define MISC_GSIOCTL 0x0e4
+#define GSIOCTL_STARTBUSY __BIT(31)
+#define GSIOCTL_GSIOMODE __BIT(30) // 0 = SPI
+#define GSIOCTL_ERROR __BIT(23)
+#define GSIOCTL_BIGENDIAN __BIT(22)
+#define GSIOCTL_GSIOGO __BIT(21)
+#define GSIOCTL_NUM_DATABYTES __BITS(17,16) // actual is + 1
+#define GSIOCTL_NUM_WAITCYCLES __BITS(15,14) // actual is + 1
+#define GSIOCTL_NUM_ADDRESSBYTES __BITS(13,12) // actual is + 1
+#define GSIOCTL_GSIOCODE __BITS(10,8)
+#define GSIOCODE_OP_RD1DATA 0
+#define GSIOCODE_OP_WRADDR_RDADDR 1
+#define GSIOCODE_OP_WRADDR_XFRDATA 2
+#define GSIOCODE_OP_WRADDR_WAIT_XFRDATA 3
+#define GSIOCODE_XFRDATA 4
+#define GSIOCTL_GSIOOP __BITS(7,0)
-#define MISC_GSIOADDRESS 0x0e8
-#define MISC_GSIODATA 0x0ec
+#define MISC_GSIOADDRESS 0x0e8
+#define MISC_GSIODATA 0x0ec
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