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[src/trunk]: src/sys/arch/arm/imx Add SPI driver.
details: https://anonhg.NetBSD.org/src/rev/a96ada99d648
branches: trunk
changeset: 327953:a96ada99d648
user: hkenken <hkenken%NetBSD.org@localhost>
date: Sat Mar 22 09:28:08 2014 +0000
description:
Add SPI driver.
i.MX51 have two eCSPI, and one CSPI.
diffstat:
sys/arch/arm/imx/files.imx51 | 14 +-
sys/arch/arm/imx/imx51_ccm.c | 25 ++-
sys/arch/arm/imx/imx51_ccmreg.h | 5 +-
sys/arch/arm/imx/imx51_spi.c | 99 +++++++++
sys/arch/arm/imx/imxcspireg.h | 93 ++++++++
sys/arch/arm/imx/imxecspireg.h | 80 +++++++
sys/arch/arm/imx/imxspi.c | 419 ++++++++++++++++++++++++++++++++++++++++
sys/arch/arm/imx/imxspireg.h | 37 +++
sys/arch/arm/imx/imxspivar.h | 80 +++++++
9 files changed, 845 insertions(+), 7 deletions(-)
diffs (truncated from 939 to 300 lines):
diff -r 54fa90910dc9 -r a96ada99d648 sys/arch/arm/imx/files.imx51
--- a/sys/arch/arm/imx/files.imx51 Sat Mar 22 08:15:25 2014 +0000
+++ b/sys/arch/arm/imx/files.imx51 Sat Mar 22 09:28:08 2014 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.imx51,v 1.7 2014/03/22 05:19:18 hkenken Exp $
+# $NetBSD: files.imx51,v 1.8 2014/03/22 09:28:08 hkenken Exp $
#
# Configuration info for the Freescale i.MX51
#
@@ -104,9 +104,15 @@
# attach imxi2c at aips with imxi2c_aips
# file arch/arm/imx/imxi2c_aips.c imxi2c_aips
-# spi bus controlloer
-# device imxspi: spibus
-# file arch/arm/imx/imx51_spi.c imxspi
+# SPI bus controlloer
+# attach of this driver need to be specified in paltform configuration
+# use flags to module version
+device imxspi : spibus
+file arch/arm/imx/imxspi.c imxspi
+defparam opt_imxspi.h IMXSPINSLAVES
+defparam opt_imxspi.h IMXSPI_DEBUG
+# attach imxspi at axi with imx51_spi
+# file arch/arm/imx/imx51_spi.c imx51_spi
# Smart Direct Memory Access Controller
# device imxsdma: dmover_service, bus_dma_generic
diff -r 54fa90910dc9 -r a96ada99d648 sys/arch/arm/imx/imx51_ccm.c
--- a/sys/arch/arm/imx/imx51_ccm.c Sat Mar 22 08:15:25 2014 +0000
+++ b/sys/arch/arm/imx/imx51_ccm.c Sat Mar 22 09:28:08 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccm.c,v 1.3 2012/09/19 07:28:38 bsh Exp $ */
+/* $NetBSD: imx51_ccm.c,v 1.4 2014/03/22 09:28:08 hkenken Exp $ */
/*
* Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.3 2012/09/19 07:28:38 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.4 2014/03/22 09:28:08 hkenken Exp $");
#include <sys/types.h>
#include <sys/time.h>
@@ -146,6 +146,7 @@
uint32_t cacrr; /* ARM clock root register */
uint32_t ccsr;
uint32_t cscdr1;
+ uint32_t cscdr2;
uint32_t cscmr1;
uint32_t cbcdr;
uint32_t cbcmr;
@@ -293,6 +294,26 @@
break;
}
return freq;
+ case IMX51CLK_CSPI_CLK_ROOT:
+ cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+ cscdr2 = bus_space_read_4(iot, ioh, CCMC_CSCDR2);
+
+ sel = __SHIFTOUT(cscmr1, CSCMR1_CSPI_CLK_SEL);
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ }
+
+ freq = freq / (1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PRED)) /
+ (1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PODF));
+
+ return freq;
default:
aprint_error_dev(ccm_softc->sc_dev,
"clock %d: not supported yet\n", clk);
diff -r 54fa90910dc9 -r a96ada99d648 sys/arch/arm/imx/imx51_ccmreg.h
--- a/sys/arch/arm/imx/imx51_ccmreg.h Sat Mar 22 08:15:25 2014 +0000
+++ b/sys/arch/arm/imx/imx51_ccmreg.h Sat Mar 22 09:28:08 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmreg.h,v 1.2 2012/09/01 00:07:32 matt Exp $ */
+/* $NetBSD: imx51_ccmreg.h,v 1.3 2014/03/22 09:28:08 hkenken Exp $ */
/*
* Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -85,6 +85,7 @@
#define CCMC_CSCMR1 0x001c
#define CSCMR1_UART_CLK_SEL_SHIFT 24
#define CSCMR1_UART_CLK_SEL_MASK __BITS(25, CSCMR1_UART_CLK_SEL_SHIFT)
+#define CSCMR1_CSPI_CLK_SEL __BITS(5, 4)
#define CCMC_CSCMR2 0x0020
#define CCMC_CSCDR1 0x0024
#define CSCDR1_UART_CLK_PRED_SHIFT 3
@@ -96,6 +97,8 @@
#define CCMC_CDCDR 0x0030
#define CCMC_CHSCCDR 0x0034 // i.MX6
#define CCMC_CSCDR2 0x0038
+#define CSCDR2_ECSPI_CLK_PRED __BITS(27, 25)
+#define CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)
#define CCMC_CSCDR3 0x003c
#define CCMC_CSCDR4 0x0040
#define CCMC_CWDR 0x0044
diff -r 54fa90910dc9 -r a96ada99d648 sys/arch/arm/imx/imx51_spi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_spi.c Sat Mar 22 09:28:08 2014 +0000
@@ -0,0 +1,99 @@
+/* $NetBSD: imx51_spi.c,v 1.1 2014/03/22 09:28:08 hkenken Exp $ */
+
+/*-
+ * Copyright (c) 2014 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_spi.c,v 1.1 2014/03/22 09:28:08 hkenken Exp $");
+
+#include "locators.h"
+#include "opt_imx.h"
+#include "opt_imxspi.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+
+#include <arm/imx/imxspivar.h>
+#include <arm/imx/imx51reg.h>
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51_ccmvar.h>
+
+struct imx51spi_softc {
+ struct imxspi_softc sc_spi;
+ struct spi_chipset_tag sc_tag;
+};
+
+CFATTACH_DECL_NEW(imx51_spi, sizeof(struct imx51spi_softc),
+ imxspi_match, imxspi_attach, NULL, NULL);
+
+static int
+imxspi_cs_enable(void *arg, int slave)
+{
+ return 0;
+}
+
+static int
+imxspi_cs_disable(void *arg, int slave)
+{
+ return 0;
+}
+
+int
+imxspi_match(device_t parent, cfdata_t cf, void *aux)
+{
+ if (strcmp(cf->cf_name, "imxspi") == 0)
+ return 1;
+
+ return 0;
+}
+
+void
+imxspi_attach(device_t parent, device_t self, void *aux)
+{
+ struct imx51spi_softc *sc = device_private(self);
+ struct axi_attach_args *aa = aux;
+ struct imxspi_attach_args saa;
+ int cf_flags = device_cfdata(self)->cf_flags;
+
+ sc->sc_tag.cookie = sc;
+ sc->sc_tag.spi_cs_enable = imxspi_cs_enable;
+ sc->sc_tag.spi_cs_disable = imxspi_cs_disable;
+
+ saa.saa_iot = aa->aa_iot;
+ saa.saa_addr = aa->aa_addr;
+ saa.saa_size = aa->aa_size;
+ saa.saa_irq = aa->aa_irq;
+ saa.saa_enhanced = cf_flags;
+
+ saa.saa_nslaves = IMXSPINSLAVES;
+ saa.saa_freq = imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT);
+ saa.saa_tag = &sc->sc_tag;
+
+ sc->sc_spi.sc_dev = self;
+
+ imxspi_attach_common(parent, &sc->sc_spi, &saa);
+}
diff -r 54fa90910dc9 -r a96ada99d648 sys/arch/arm/imx/imxcspireg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imxcspireg.h Sat Mar 22 09:28:08 2014 +0000
@@ -0,0 +1,93 @@
+/* $NetBSD: imxcspireg.h,v 1.1 2014/03/22 09:28:08 hkenken Exp $ */
+
+/*
+ * Copyright (c) 2014 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_IMX_IMXCSPIREG_H_
+#define _ARM_IMX_IMXCSPIREG_H_
+
+#define CSPI_RXDATA 0x00
+#define CSPI_TXDATA 0x04
+#define CSPI_CONREG 0x08
+#ifdef IMX51
+#define CSPI_CON_CS __BITS(13, 12)
+#define CSPI_CON_DRCTL __BITS( 9, 8)
+#define CSPI_CON_BITCOUNT __BITS(31, 20)
+#else
+#define CSPI_CON_CS __BITS(25, 24)
+#define CSPI_CON_DRCTL __BITS(21, 20)
+#define CSPI_CON_BITCOUNT __BITS(12, 8)
+#endif
+#define CSPI_CON_DIV __BITS(18, 16)
+#define CSPI_CON_SSPOL __BIT(7) /* SPI SS Polarity Select */
+#define CSPI_CON_SSCTL __BIT(6) /* In master mode, this bit
+ * selects the output wave form
+ * for the SS signal.
+ */
+#define CSPI_CON_PHA __BIT(5) /* PHA */
+#define CSPI_CON_POL __BIT(4) /* POL */
+#define CSPI_CON_SMC __BIT(3) /* SMC */
+#define CSPI_CON_XCH __BIT(2) /* XCH */
+#define CSPI_CON_MODE __BIT(1) /* MODE */
+#define CSPI_CON_ENABLE __BIT(0) /* EN */
+#define CSPI_INTREG 0x0c
+#define CSPI_INTR_ALL_EN 0x000001ff /* All Intarruption Enabled */
+#ifdef IMX51
+#define CSPI_INTR_TC_EN __BIT(7) /* TX Complete */
+#else
+#define CSPI_INTR_TC_EN __BIT(8) /* TX Complete */
+#define CSPI_INTR_BO_EN __BIT(7) /* Bit Counter Overflow */
+#endif
+#define CSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */
+#define CSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */
+#define CSPI_INTR_RH_EN __BIT(4) /* RXFIFO Half Full */
+#define CSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */
+#define CSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */
+#define CSPI_INTR_TH_EN __BIT(1) /* TXFIFO Half Empty */
+#define CSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */
+#define CSPI_DMAREG 0x10
+#define CSPI_STATREG 0x14
+#ifdef IMX51
+#define CSPI_STAT_CLR_TC __BIT(7) /* Clear TC of status register */
+#define CSPI_STAT_CLR CSPI_STAT_CLR_TC
+#else
+#define CSPI_STAT_CLR_TC __BIT(8) /* Clear TC of status register */
+#define CSPI_STAT_CLR_BO __BIT(7) /* Clear BO of status register */
+#define CSPI_STAT_CLR (CSPI_STAT_CLR_TC | CSPI_STAT_CLR_BO)
+#endif
+#define CSPI_STAT_RO __BIT(6) /* RXFIFO Overflow */
+#define CSPI_STAT_RF __BIT(5) /* RXFIFO Full */
+#define CSPI_STAT_RH __BIT(4) /* RXFIFO Half Full */
+#define CSPI_STAT_RR __BIT(3) /* RXFIFO Ready */
+#define CSPI_STAT_TF __BIT(2) /* TXFIFO Full */
+#define CSPI_STAT_TH __BIT(1) /* TXFIFO Half Empty */
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