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[src/trunk]: src/sys/dev/marvell Support Armada 370 and DDR3 tags.
details: https://anonhg.NetBSD.org/src/rev/d603a5f404d3
branches: trunk
changeset: 327725:d603a5f404d3
user: kiyohara <kiyohara%NetBSD.org@localhost>
date: Sat Mar 15 13:33:48 2014 +0000
description:
Support Armada 370 and DDR3 tags.
diffstat:
sys/dev/marvell/ehci_mv.c | 24 +++------
sys/dev/marvell/gtidmac.c | 114 ++++++++++++++++++++++++------------------
sys/dev/marvell/gtidmacvar.h | 22 +++++++-
sys/dev/marvell/if_mvgbe.c | 31 +++++------
sys/dev/marvell/mvpex.c | 52 +++++++++---------
sys/dev/marvell/mvpexvar.h | 4 +-
sys/dev/marvell/mvsata_mv.c | 23 +++----
sys/dev/marvell/mvsdio.c | 18 +----
8 files changed, 154 insertions(+), 134 deletions(-)
diffs (truncated from 669 to 300 lines):
diff -r e0209cb4b7e3 -r d603a5f404d3 sys/dev/marvell/ehci_mv.c
--- a/sys/dev/marvell/ehci_mv.c Sat Mar 15 12:20:09 2014 +0000
+++ b/sys/dev/marvell/ehci_mv.c Sat Mar 15 13:33:48 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ehci_mv.c,v 1.4 2013/09/08 04:10:23 kiyohara Exp $ */
+/* $NetBSD: ehci_mv.c,v 1.5 2014/03/15 13:33:48 kiyohara Exp $ */
/*
* Copyright (c) 2008 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ehci_mv.c,v 1.4 2013/09/08 04:10:23 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ehci_mv.c,v 1.5 2014/03/15 13:33:48 kiyohara Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -164,8 +164,8 @@
static int mvusb_match(device_t, cfdata_t, void *);
static void mvusb_attach(device_t, device_t, void *);
-static void mvusb_init(struct mvusb_softc *);
-static void mvusb_wininit(struct mvusb_softc *);
+static void mvusb_init(struct mvusb_softc *, enum marvell_tags *);
+static void mvusb_wininit(struct mvusb_softc *, enum marvell_tags *);
static void mvusb_vendor_init(struct ehci_softc *);
static int mvusb_vendor_port_status(struct ehci_softc *, uint32_t, int);
@@ -216,7 +216,7 @@
aprint_error_dev(self, "can't map registers\n");
return;
}
- mvusb_init(sc);
+ mvusb_init(sc, mva->mva_tags);
/* Map I/O registers for ehci */
sc->sc.sc_size = MARVELL_USB_EHCI_SIZE;
@@ -254,7 +254,7 @@
}
static void
-mvusb_init(struct mvusb_softc *sc)
+mvusb_init(struct mvusb_softc *sc, enum marvell_tags *tags)
{
uint32_t reg;
int opr_offs;
@@ -357,24 +357,16 @@
reg);
}
- mvusb_wininit(sc);
+ mvusb_wininit(sc, tags);
}
static void
-mvusb_wininit(struct mvusb_softc *sc)
+mvusb_wininit(struct mvusb_softc *sc, enum marvell_tags *tags)
{
device_t pdev = device_parent(sc->sc.sc_dev);
uint64_t base;
uint32_t size;
int window, target, attr, rv, i;
- static int tags[] = {
- MARVELL_TAG_SDRAM_CS0,
- MARVELL_TAG_SDRAM_CS1,
- MARVELL_TAG_SDRAM_CS2,
- MARVELL_TAG_SDRAM_CS3,
-
- MARVELL_TAG_UNDEFINED,
- };
for (window = 0, i = 0;
tags[i] != MARVELL_TAG_UNDEFINED && window < MARVELL_USB_NWINDOW;
diff -r e0209cb4b7e3 -r d603a5f404d3 sys/dev/marvell/gtidmac.c
--- a/sys/dev/marvell/gtidmac.c Sat Mar 15 12:20:09 2014 +0000
+++ b/sys/dev/marvell/gtidmac.c Sat Mar 15 13:33:48 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gtidmac.c,v 1.10 2013/09/28 05:39:06 kiyohara Exp $ */
+/* $NetBSD: gtidmac.c,v 1.11 2014/03/15 13:33:48 kiyohara Exp $ */
/*
* Copyright (c) 2008, 2012 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gtidmac.c,v 1.10 2013/09/28 05:39:06 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtidmac.c,v 1.11 2014/03/15 13:33:48 kiyohara Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -162,8 +162,8 @@
static uint32_t gtidmac_finish(void *, int, int);
static uint32_t mvxore_finish(void *, int, int);
-static void gtidmac_wininit(struct gtidmac_softc *);
-static void mvxore_wininit(struct gtidmac_softc *);
+static void gtidmac_wininit(struct gtidmac_softc *, enum marvell_tags *);
+static void mvxore_wininit(struct gtidmac_softc *, enum marvell_tags *);
static int gtidmac_buffer_setup(struct gtidmac_softc *);
static int mvxore_buffer_setup(struct gtidmac_softc *);
@@ -325,6 +325,9 @@
{ MARVELL_ARMADAXP_MV78460, 0, -1, 2, 94 },
};
+struct gtidmac_winacctbl *gtidmac_winacctbl;
+struct gtidmac_winacctbl *mvxore_winacctbl;
+
CFATTACH_DECL_NEW(gtidmac_gt, sizeof(struct gtidmac_softc),
gtidmac_match, gtidmac_attach, NULL, NULL);
CFATTACH_DECL_NEW(gtidmac_mbus, sizeof(struct gtidmac_softc),
@@ -460,7 +463,7 @@
goto fail4;
if (mva->mva_model != MARVELL_DISCOVERY)
- gtidmac_wininit(sc);
+ gtidmac_wininit(sc, mva->mva_tags);
/* Setup interrupt */
for (i = 0; i < GTIDMAC_NINTRRUPT; i++) {
@@ -497,7 +500,7 @@
(i & 0x2) ? mvxore_port1_intr : mvxore_port0_intr,
sc);
- mvxore_wininit(sc);
+ mvxore_wininit(sc, mva->mva_tags);
/* Register us with dmover. */
sc->sc_dmb_xore.dmb_name = device_xname(sc->sc_dev);
@@ -1477,36 +1480,18 @@
}
static void
-gtidmac_wininit(struct gtidmac_softc *sc)
+gtidmac_wininit(struct gtidmac_softc *sc, enum marvell_tags *tags)
{
device_t pdev = device_parent(sc->sc_dev);
uint64_t base;
- uint32_t size, cxap, en;
- int window, target, attr, rv, i;
- struct {
- int tag;
- int winacc;
- } targets[] = {
- { MARVELL_TAG_SDRAM_CS0, GTIDMAC_CXAPR_WINACC_FA },
- { MARVELL_TAG_SDRAM_CS1, GTIDMAC_CXAPR_WINACC_FA },
- { MARVELL_TAG_SDRAM_CS2, GTIDMAC_CXAPR_WINACC_FA },
- { MARVELL_TAG_SDRAM_CS3, GTIDMAC_CXAPR_WINACC_FA },
-
- /* Also can set following targets. */
- /* Devices = 0x1(ORION_TARGETID_DEVICE_*) */
- /* PCI = 0x3(ORION_TARGETID_PCI0_*) */
- /* PCI Express = 0x4(ORION_TARGETID_PEX?_*) */
- /* Tunit SRAM(?) = 0x5(???) */
-
- { MARVELL_TAG_UNDEFINED, GTIDMAC_CXAPR_WINACC_NOAA }
- };
+ uint32_t size, cxap, en, winacc;
+ int window, target, attr, rv, i, j;
en = 0xff;
cxap = 0;
for (window = 0, i = 0;
- targets[i].tag != MARVELL_TAG_UNDEFINED && window < GTIDMAC_NWINDOW;
- i++) {
- rv = marvell_winparams_by_tag(pdev, targets[i].tag,
+ tags[i] != MARVELL_TAG_UNDEFINED && window < GTIDMAC_NWINDOW; i++) {
+ rv = marvell_winparams_by_tag(pdev, tags[i],
&target, &attr, &base, &size);
if (rv != 0 || size == 0)
continue;
@@ -1527,7 +1512,30 @@
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIDMAC_SRX(window),
GTIDMAC_SRX_SIZE(size));
en &= ~GTIDMAC_BAER_EN(window);
- cxap |= GTIDMAC_CXAPR_WINACC(window, targets[i].winacc);
+
+ winacc = GTIDMAC_CXAPR_WINACC_FA;
+ if (gtidmac_winacctbl != NULL)
+ for (j = 0;
+ gtidmac_winacctbl[j].tag != MARVELL_TAG_UNDEFINED;
+ j++) {
+ if (gtidmac_winacctbl[j].tag != tags[i])
+ continue;
+
+ switch (gtidmac_winacctbl[j].winacc) {
+ case GTIDMAC_WINACC_NOACCESSALLOWED:
+ winacc = GTIDMAC_CXAPR_WINACC_NOAA;
+ break;
+ case GTIDMAC_WINACC_READONLY:
+ winacc = GTIDMAC_CXAPR_WINACC_RO;
+ break;
+ case GTIDMAC_WINACC_FULLACCESS:
+ default: /* XXXX: default is full access */
+ break;
+ }
+ break;
+ }
+ cxap |= GTIDMAC_CXAPR_WINACC(window, winacc);
+
window++;
}
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIDMAC_BAER, en);
@@ -1538,29 +1546,17 @@
}
static void
-mvxore_wininit(struct gtidmac_softc *sc)
+mvxore_wininit(struct gtidmac_softc *sc, enum marvell_tags *tags)
{
device_t pdev = device_parent(sc->sc_dev);
uint64_t base;
- uint32_t target, attr, size, xexwc;
- int window, rv, i, p;
- struct {
- int tag;
- int winacc;
- } targets[] = {
- { MARVELL_TAG_SDRAM_CS0, MVXORE_XEXWCR_WINACC_FA },
- { MARVELL_TAG_SDRAM_CS1, MVXORE_XEXWCR_WINACC_FA },
- { MARVELL_TAG_SDRAM_CS2, MVXORE_XEXWCR_WINACC_FA },
- { MARVELL_TAG_SDRAM_CS3, MVXORE_XEXWCR_WINACC_FA },
-
- { MARVELL_TAG_UNDEFINED, MVXORE_XEXWCR_WINACC_NOAA }
- };
+ uint32_t target, attr, size, xexwc, winacc;
+ int window, rv, i, j, p;
xexwc = 0;
for (window = 0, i = 0;
- targets[i].tag != MARVELL_TAG_UNDEFINED && window < MVXORE_NWINDOW;
- i++) {
- rv = marvell_winparams_by_tag(pdev, targets[i].tag,
+ tags[i] != MARVELL_TAG_UNDEFINED && window < MVXORE_NWINDOW; i++) {
+ rv = marvell_winparams_by_tag(pdev, tags[i],
&target, &attr, &base, &size);
if (rv != 0 || size == 0)
continue;
@@ -1587,8 +1583,30 @@
MVXORE_XESMRX(sc, p, window),
MVXORE_XESMRX_SIZE(size));
}
+
+ winacc = MVXORE_XEXWCR_WINACC_FA;
+ if (mvxore_winacctbl != NULL)
+ for (j = 0;
+ mvxore_winacctbl[j].tag != MARVELL_TAG_UNDEFINED;
+ j++) {
+ if (gtidmac_winacctbl[j].tag != tags[i])
+ continue;
+
+ switch (gtidmac_winacctbl[j].winacc) {
+ case GTIDMAC_WINACC_NOACCESSALLOWED:
+ winacc = MVXORE_XEXWCR_WINACC_NOAA;
+ break;
+ case GTIDMAC_WINACC_READONLY:
+ winacc = MVXORE_XEXWCR_WINACC_RO;
+ break;
+ case GTIDMAC_WINACC_FULLACCESS:
+ default: /* XXXX: default is full access */
+ break;
+ }
+ break;
+ }
xexwc |= (MVXORE_XEXWCR_WINEN(window) |
- MVXORE_XEXWCR_WINACC(window, targets[i].winacc));
+ MVXORE_XEXWCR_WINACC(window, winacc));
window++;
}
diff -r e0209cb4b7e3 -r d603a5f404d3 sys/dev/marvell/gtidmacvar.h
--- a/sys/dev/marvell/gtidmacvar.h Sat Mar 15 12:20:09 2014 +0000
+++ b/sys/dev/marvell/gtidmacvar.h Sat Mar 15 13:33:48 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gtidmacvar.h,v 1.1 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtidmacvar.h,v 1.2 2014/03/15 13:33:48 kiyohara Exp $ */
/*
* Copyright (c) 2008, 2009 KIYOHARA Takashi
* All rights reserved.
@@ -28,6 +28,26 @@
#ifndef _GTIDMACVAR_H_
#define _GTIDMACVAR_H_
+#include <dev/marvell/marvellvar.h>
+
+/*
+ * We get access control of IDMAC.
+ * Please set to variable 'gtidmac_winacctbl' your winacctbl-list by
+ * device_register() or MD initialization processing. You can also set except
+ * MARVELL_TAG_SDRAM_CS* to a tag. In this case, device_register() should
+ * replace mva_tags of marvell_attach_args to the tag list for you.
+ */
+struct gtidmac_winacctbl {
+ enum marvell_tags tag;
+
+#define GTIDMAC_WINACC_NOACCESSALLOWED 0 /* No Access Allowed */
+#define GTIDMAC_WINACC_READONLY 1 /* Read Only */
+#define GTIDMAC_WINACC_FULLACCESS 2 /* Full Access */
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