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[src/trunk]: src/sys/lib/libunwind Add a dummy element as explicit padding fo...



details:   https://anonhg.NetBSD.org/src/rev/1b0b3634e507
branches:  trunk
changeset: 327586:1b0b3634e507
user:      joerg <joerg%NetBSD.org@localhost>
date:      Wed Mar 12 00:01:12 2014 +0000

description:
Add a dummy element as explicit padding for PPC32. Fix DWARF enumeration
to match the values created by GCC. Fix DWARFish -> index conversion.

diffstat:

 sys/lib/libunwind/Registers.hpp      |  29 ++++++----
 sys/lib/libunwind/unwind_registers.S |  98 ++++++++++++++++++++++++++++-------
 2 files changed, 96 insertions(+), 31 deletions(-)

diffs (187 lines):

diff -r 8ed7c8b649e0 -r 1b0b3634e507 sys/lib/libunwind/Registers.hpp
--- a/sys/lib/libunwind/Registers.hpp   Tue Mar 11 23:57:42 2014 +0000
+++ b/sys/lib/libunwind/Registers.hpp   Wed Mar 12 00:01:12 2014 +0000
@@ -144,19 +144,18 @@
   DWARF_PPC32_R31 = 31,
   DWARF_PPC32_F0 = 32,
   DWARF_PPC32_F31 = 63,
-  DWARF_PPC32_V0 = 1124,
-  DWARF_PPC32_V31 = 1155,
   DWARF_PPC32_LR = 65,
-  DWARF_PPC32_CTR = 66,
-  DWARF_PPC32_XER = 76,
+  DWARF_PPC32_CR = 70,
+  DWARF_PPC32_V0 = 77,
+  DWARF_PPC32_V31 = 108,
+
   REGNO_PPC32_R0 = 0,
-  REGNO_PPC32_R1 = 0,
+  REGNO_PPC32_R1 = 1,
   REGNO_PPC32_R31 = 31,
-  REGNO_PPC32_CR = 32,
-  REGNO_PPC32_LR = 33,
-  REGNO_PPC32_CTR = 34,
-  REGNO_PPC32_XER = 35,
-  REGNO_PPC32_SRR0 = 36,
+  REGNO_PPC32_LR = 32,
+  REGNO_PPC32_CR = 33,
+  REGNO_PPC32_SRR0 = 34,
+
   REGNO_PPC32_F0 = REGNO_PPC32_SRR0 + 1,
   REGNO_PPC32_F31 = REGNO_PPC32_F0 + 31,
   REGNO_PPC32_V0 = REGNO_PPC32_F31 + 1,
@@ -180,7 +179,14 @@
       return REGNO_PPC32_F0 + (num - DWARF_PPC32_F0);
     if (num >= DWARF_PPC32_V0 && num <= DWARF_PPC32_V31)
       return REGNO_PPC32_V0 + (num - DWARF_PPC32_V0);
-    return LAST_REGISTER + 1;
+    switch (num) {
+    case DWARF_PPC32_LR:
+      return REGNO_PPC32_LR;
+    case DWARF_PPC32_CR:
+      return REGNO_PPC32_CR;
+    default:
+      return LAST_REGISTER + 1;
+    }
   }
 
   bool validRegister(int num) const {
@@ -225,6 +231,7 @@
     uint64_t low, high;
   };
   uint32_t reg[REGNO_PPC32_SRR0 + 1];
+  uint32_t dummy;
   uint64_t fpreg[32];
   vecreg_t vecreg[64];
 };
diff -r 8ed7c8b649e0 -r 1b0b3634e507 sys/lib/libunwind/unwind_registers.S
--- a/sys/lib/libunwind/unwind_registers.S      Tue Mar 11 23:57:42 2014 +0000
+++ b/sys/lib/libunwind/unwind_registers.S      Wed Mar 12 00:01:12 2014 +0000
@@ -116,6 +116,7 @@
 #ifdef __powerpc__
        .hidden _ZN7_Unwind15Registers_ppc32C1Ev
 ENTRY(_ZN7_Unwind15Registers_ppc32C1Ev)
+       /* TODO: skip non-callee-safe registers */
        stw              %r0,  0(%r3)
        stw              %r1,  4(%r3)
        stw              %r2,  8(%r3)
@@ -148,21 +149,82 @@
        stw             %r29,116(%r3)
        stw             %r30,120(%r3)
        stw             %r31,124(%r3)
-
+       mflr            %r0
+       stw             %r0, 136(%r3) /* SRR0 */
        mfcr            %r0
-       stw             %r0, 128(%r3) /* CR */
-       mflr            %r0
-       stw             %r0, 132(%r3) /* LR */
-       stw             %r0, 144(%r3) /* LR */
-       mfctr           %r0
-       stw             %r0, 136(%r3) /* CTR */
-       mfxer           %r0
-       stw             %r0, 140(%r3) /*  XER */
+       stw             %r0, 132(%r3) /* CR */
 
+       stfd             %f0, 144(%r3)
+       stfd             %f1, 152(%r3)
+       stfd             %f2, 160(%r3)
+       stfd             %f3, 168(%r3)
+       stfd             %f4, 176(%r3)
+       stfd             %f5, 184(%r3)
+       stfd             %f6, 192(%r3)
+       stfd             %f7, 200(%r3)
+       stfd             %f8, 208(%r3)
+       stfd             %f9, 216(%r3)
+       stfd            %f10, 224(%r3)
+       stfd            %f11, 232(%r3)
+       stfd            %f12, 240(%r3)
+       stfd            %f13, 248(%r3)
+       stfd            %f14, 256(%r3)
+       stfd            %f15, 264(%r3)
+       stfd            %f16, 272(%r3)
+       stfd            %f17, 280(%r3)
+       stfd            %f18, 288(%r3)
+       stfd            %f19, 296(%r3)
+       stfd            %f20, 304(%r3)
+       stfd            %f21, 312(%r3)
+       stfd            %f22, 320(%r3)
+       stfd            %f23, 328(%r3)
+       stfd            %f24, 336(%r3)
+       stfd            %f25, 344(%r3)
+       stfd            %f26, 352(%r3)
+       stfd            %f27, 360(%r3)
+       stfd            %f28, 368(%r3)
+       stfd            %f29, 376(%r3)
+       stfd            %f30, 384(%r3)
+       stfd            %f31, 392(%r3)
+
+       /* LR is undefined */
        blr
 
        .hidden _ZNK7_Unwind15Registers_ppc326jumptoEv
 ENTRY(_ZNK7_Unwind15Registers_ppc326jumptoEv)
+       lfd              %f0, 144(%r3)
+       lfd              %f1, 152(%r3)
+       lfd              %f2, 160(%r3)
+       lfd              %f3, 168(%r3)
+       lfd              %f4, 176(%r3)
+       lfd              %f5, 184(%r3)
+       lfd              %f6, 192(%r3)
+       lfd              %f7, 200(%r3)
+       lfd              %f8, 208(%r3)
+       lfd              %f9, 216(%r3)
+       lfd             %f10, 224(%r3)
+       lfd             %f11, 232(%r3)
+       lfd             %f12, 240(%r3)
+       lfd             %f13, 248(%r3)
+       lfd             %f14, 256(%r3)
+       lfd             %f15, 264(%r3)
+       lfd             %f16, 272(%r3)
+       lfd             %f17, 280(%r3)
+       lfd             %f18, 288(%r3)
+       lfd             %f19, 296(%r3)
+       lfd             %f20, 304(%r3)
+       lfd             %f21, 312(%r3)
+       lfd             %f22, 320(%r3)
+       lfd             %f23, 328(%r3)
+       lfd             %f24, 336(%r3)
+       lfd             %f25, 344(%r3)
+       lfd             %f26, 352(%r3)
+       lfd             %f27, 360(%r3)
+       lfd             %f28, 368(%r3)
+       lfd             %f29, 376(%r3)
+       lfd             %f30, 384(%r3)
+       lfd             %f31, 392(%r3)
+
        lwz              %r2, 8(%r3)
        /* skip r3 for now */
        lwz              %r4, 16(%r3)
@@ -194,20 +256,16 @@
        lwz             %r30,120(%r3)
        lwz             %r31,124(%r3)
 
-       lwz             %r0, 128(%r3) /* CR */
-       mtcr            %r0
-       lwz             %r0, 132(%r3) /* LR */
+       lwz             %r0, 128(%r3) /* LR */
        mtlr            %r0
-       lwz             %r0, 136(%r3) /* CTR */
-       mtctr           %r0
-       lwz             %r0, 140(%r3) /*  XER */
-       mtxer           %r0
-       lwz             %r0, 144(%r3) /* SRR0 ? */
+       lwz             %r0, 132(%r3) /* CR */
+       mtcr            %r0
+       lwz             %r0, 136(%r3) /* SRR0 */
        mtctr           %r0
 
-       lwz             %r0, 0(%r3)   /* do r0 now */
-       lwz             %r1,4(%r3)    /* do sp now */
-       lwz             %r3,12(%r3)   /* do r3 last */
+       lwz             %r0,  0(%r3)   /* do r0 now */
+       lwz             %r1,  4(%r3)   /* do sp now */
+       lwz             %r3, 12(%r3)   /* do r3 last */
        bctr
 #endif
 



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