[src/trunk]: src/sys/arch/x86/include Add the XCR bits for snazzy upcoming fe...

[dsl <dsl%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8ea126b53127
branches:  trunk
changeset: 327018:8ea126b53127
user:      dsl <dsl%NetBSD.org@localhost>
date:      Tue Feb 25 22:11:11 2014 +0000

description:
Add the XCR bits for snazzy upcoming features.
Define a mask for the fpu releated ones - only these wll be enabled.
The memory bound ones will need saving on every context switch.

diffstat:

 sys/arch/x86/include/specialreg.h |  24 +++++++++++++++++++++---
 1 files changed, 21 insertions(+), 3 deletions(-)

diffs (40 lines):

diff -r 17e0b2318a18 -r 8ea126b53127 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Tue Feb 25 21:29:12 2014 +0000
+++ b/sys/arch/x86/include/specialreg.h Tue Feb 25 22:11:11 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.77 2014/01/04 21:09:39 msaitoh Exp $  */
+/*     $NetBSD: specialreg.h,v 1.78 2014/02/25 22:11:11 dsl Exp $      */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -93,10 +93,28 @@
  */
 #define        XCR0_X87        0x00000001      /* x87 FPU/MMX state */
 #define        XCR0_SSE        0x00000002      /* SSE state */
-#define        XCR0_AVX        0x00000004      /* AVX state (ymmn registers) */
+#define        XCR0_YMM_Hi128  0x00000004      /* AVX-256 (ymmn registers) */
+#define        XCR0_BNDREGS    0x00000008      /* Memory protection ext bounds */
+#define        XCR0_BNDCSR     0x00000010      /* Memory protection ext state */
+#define        XCR0_Opmask     0x00000020      /* AVX-512 Opmask */
+#define        XCR0_ZMM_Hi256  0x00000040      /* AVX-512 upper 256 bits low regs */
+#define        XCR0_Hi16_ZMM   0x00000080      /* AVX-512 512 bits upper registers */
+
+/*
+ * Known fpu bits - only these get enabled
+ * I think the XCR0_BNDREGS and XCR0_BNDCSR would need saving on
+ * every context switch.
+ * The save are is sized for all the fields below (max 2680 bytes).
+ */
+#define XCR0_FPU       (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
+                       XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
+
+#define XCR0_BND       (XCR0_BNDREGS | XCR0_BNDCSR)
 
 #define XCR0_FLAGS1    "\20" \
-       "\1" "x87"      "\2" "SSE"      "\3" "AVX"      "\4" "B03"
+       "\1" "x87"      "\2" "SSE"      "\3" "AVX" \
+       "\4" "BNDREGS"  "\5" "BNDCSR" \
+       "\6" "Opmask"   "\7" "ZMM_Hi256" "\10" "Hi16_ZMM"
 
 
 /*