[src/trunk]: src/sys/arch/arm/include Make the tlb_flush*SE take a vaddr_t, n...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d4f06c7bc4ce
branches:  trunk
changeset: 326855:d4f06c7bc4ce
user:      matt <matt%NetBSD.org@localhost>
date:      Thu Feb 20 17:19:55 2014 +0000

description:
Make the tlb_flush*SE take a vaddr_t, not a u_int.

diffstat:

 sys/arch/arm/include/cpufunc.h |  49 ++++++++++++++++++++++++------------------
 1 files changed, 28 insertions(+), 21 deletions(-)

diffs (155 lines):

diff -r d54f782a89d8 -r d4f06c7bc4ce sys/arch/arm/include/cpufunc.h
--- a/sys/arch/arm/include/cpufunc.h    Thu Feb 20 16:33:23 2014 +0000
+++ b/sys/arch/arm/include/cpufunc.h    Thu Feb 20 17:19:55 2014 +0000
@@ -67,11 +67,11 @@
        /* TLB functions */
 
        void    (*cf_tlb_flushID)       (void);
-       void    (*cf_tlb_flushID_SE)    (u_int);
+       void    (*cf_tlb_flushID_SE)    (vaddr_t);
        void    (*cf_tlb_flushI)        (void);
-       void    (*cf_tlb_flushI_SE)     (u_int);
+       void    (*cf_tlb_flushI_SE)     (vaddr_t);
        void    (*cf_tlb_flushD)        (void);
-       void    (*cf_tlb_flushD_SE)     (u_int);
+       void    (*cf_tlb_flushD_SE)     (vaddr_t);
 
        /*
         * Cache operations:
@@ -258,7 +258,7 @@
 void   arm7tdmi_setup          (char *);
 void   arm7tdmi_setttb         (u_int, bool);
 void   arm7tdmi_tlb_flushID    (void);
-void   arm7tdmi_tlb_flushID_SE (u_int);
+void   arm7tdmi_tlb_flushID_SE (vaddr_t);
 void   arm7tdmi_cache_flushID  (void);
 void   arm7tdmi_context_switch (u_int);
 #endif /* CPU_ARM7TDMI */
@@ -266,7 +266,7 @@
 #ifdef CPU_ARM8
 void   arm8_setttb             (u_int, bool);
 void   arm8_tlb_flushID        (void);
-void   arm8_tlb_flushID_SE     (u_int);
+void   arm8_tlb_flushID_SE     (vaddr_t);
 void   arm8_cache_flushID      (void);
 void   arm8_cache_flushID_E    (u_int);
 void   arm8_cache_cleanID      (void);
@@ -293,8 +293,8 @@
 void   fa526_setttb            (u_int, bool);
 void   fa526_context_switch    (u_int);
 void   fa526_cpu_sleep         (int);
-void   fa526_tlb_flushI_SE     (u_int);
-void   fa526_tlb_flushID_SE    (u_int);
+void   fa526_tlb_flushI_SE     (vaddr_t);
+void   fa526_tlb_flushID_SE    (vaddr_t);
 void   fa526_flush_prefetchbuf (void);
 void   fa526_flush_brnchtgt_E  (u_int);
 
@@ -325,12 +325,12 @@
 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
 void   sa1_setttb              (u_int, bool);
 
-void   sa1_tlb_flushID_SE      (u_int);
+void   sa1_tlb_flushID_SE      (vaddr_t);
 
 void   sa1_cache_flushID       (void);
 void   sa1_cache_flushI        (void);
 void   sa1_cache_flushD        (void);
-void   sa1_cache_flushD_SE     (u_int);
+void   sa1_cache_flushD_SE     (vaddr_t);
 
 void   sa1_cache_cleanID       (void);
 void   sa1_cache_cleanD        (void);
@@ -353,7 +353,7 @@
 #ifdef CPU_ARM9
 void   arm9_setttb             (u_int, bool);
 
-void   arm9_tlb_flushID_SE     (u_int);
+void   arm9_tlb_flushID_SE     (vaddr_t);
 
 void   arm9_icache_sync_all    (void);
 void   arm9_icache_sync_range  (vaddr_t, vsize_t);
@@ -377,8 +377,8 @@
 #endif
 
 #if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA)
-void   arm10_tlb_flushID_SE    (u_int);
-void   arm10_tlb_flushI_SE     (u_int);
+void   arm10_tlb_flushID_SE    (vaddr_t);
+void   arm10_tlb_flushI_SE     (vaddr_t);
 
 void   arm10_context_switch    (u_int);
 
@@ -427,9 +427,6 @@
 #if defined(CPU_ARM11) || defined(CPU_CORTEX)
 void   arm11_setttb            (u_int, bool);
 
-void   arm11_tlb_flushID_SE    (u_int);
-void   arm11_tlb_flushI_SE     (u_int);
-
 void   arm11_context_switch    (u_int);
 
 void   arm11_cpu_sleep         (int);
@@ -437,7 +434,9 @@
 void   arm11_tlb_flushID       (void);
 void   arm11_tlb_flushI        (void);
 void   arm11_tlb_flushD        (void);
-void   arm11_tlb_flushD_SE     (u_int va);
+void   arm11_tlb_flushID_SE    (vaddr_t);
+void   arm11_tlb_flushI_SE     (vaddr_t);
+void   arm11_tlb_flushD_SE     (vaddr_t);
 
 void   armv11_dcache_wbinv_all (void);
 void   armv11_idcache_wbinv_all(void);
@@ -469,9 +468,17 @@
 void   armv7_idcache_wbinv_range(vaddr_t, vsize_t);
 
 void   armv7_icache_sync_all(void);
+
+void   armv7_tlb_flushID(void);
+void   armv7_tlb_flushI(void);
+void   armv7_tlb_flushD(void);
+
+void   armv7_tlb_flushID_SE(vaddr_t);
+void   armv7_tlb_flushI_SE(vaddr_t);
+void   armv7_tlb_flushD_SE(vaddr_t);
+
 void   armv7_cpu_sleep(int);
 void   armv7_context_switch(u_int);
-void   armv7_tlb_flushID_SE(u_int);
 void   armv7_drain_writebuf(void);
 void   armv7_setup(char *string);
 #endif
@@ -484,7 +491,7 @@
 #if defined(CPU_PJ4B)
 void   pj4b_setttb(u_int, bool);
 void   pj4b_tlb_flushID(void);
-void   pj4b_tlb_flushID_SE(u_int);
+void   pj4b_tlb_flushID_SE(vaddr_t);
 
 void   pj4b_icache_sync_range(vm_offset_t, vm_size_t);
 void   pj4b_idcache_wbinv_range(vm_offset_t, vm_size_t);
@@ -530,7 +537,7 @@
 void   armv4_tlb_flushID       (void);
 void   armv4_tlb_flushI        (void);
 void   armv4_tlb_flushD        (void);
-void   armv4_tlb_flushD_SE     (u_int);
+void   armv4_tlb_flushD_SE     (vaddr_t);
 
 void   armv4_drain_writebuf    (void);
 #endif
@@ -554,12 +561,12 @@
 
 void   xscale_setttb           (u_int, bool);
 
-void   xscale_tlb_flushID_SE   (u_int);
+void   xscale_tlb_flushID_SE   (vaddr_t);
 
 void   xscale_cache_flushID    (void);
 void   xscale_cache_flushI     (void);
 void   xscale_cache_flushD     (void);
-void   xscale_cache_flushD_SE  (u_int);
+void   xscale_cache_flushD_SE  (vaddr_t);
 
 void   xscale_cache_cleanID    (void);
 void   xscale_cache_cleanD     (void);