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[src/trunk]: src Move sys/arch/amd64/amd64/fpu.c and sys/arch/amd64/include/f...
details: https://anonhg.NetBSD.org/src/rev/0cf020bd62e0
branches: trunk
changeset: 326674:0cf020bd62e0
user: dsl <dsl%NetBSD.org@localhost>
date: Tue Feb 11 20:17:16 2014 +0000
description:
Move sys/arch/amd64/amd64/fpu.c and sys/arch/amd64/include/fpu.h
into sys/arch/x86 in preparation for using the same code for i386.
diffstat:
distrib/sets/lists/comp/md.amd64 | 5 +-
sys/arch/amd64/amd64/fpu.c | 484 ----------------------------
sys/arch/amd64/amd64/machdep.c | 6 +-
sys/arch/amd64/amd64/netbsd32_machdep.c | 6 +-
sys/arch/amd64/amd64/process_machdep.c | 6 +-
sys/arch/amd64/amd64/trap.c | 6 +-
sys/arch/amd64/conf/files.amd64 | 4 +-
sys/arch/amd64/include/Makefile | 4 +-
sys/arch/amd64/include/fenv.h | 4 +-
sys/arch/amd64/include/fpu.h | 25 -
sys/arch/amd64/include/frame.h | 4 +-
sys/arch/amd64/include/pcb.h | 4 +-
sys/arch/amd64/include/reg.h | 4 +-
sys/arch/x86/acpi/acpi_wakeup.c | 11 +-
sys/arch/x86/include/Makefile | 3 +-
sys/arch/x86/include/fpu.h | 25 +
sys/arch/x86/x86/fpu.c | 484 ++++++++++++++++++++++++++++
sys/arch/x86/x86/ipi.c | 6 +-
sys/arch/x86/x86/vm_machdep.c | 8 +-
sys/arch/xen/conf/files.xen | 4 +-
sys/arch/xen/x86/cpu.c | 6 +-
sys/arch/xen/x86/xen_ipi.c | 8 +-
sys/compat/linux/arch/amd64/linux_machdep.c | 5 +-
23 files changed, 557 insertions(+), 565 deletions(-)
diffs (truncated from 1490 to 300 lines):
diff -r 379104c0dafe -r 0cf020bd62e0 distrib/sets/lists/comp/md.amd64
--- a/distrib/sets/lists/comp/md.amd64 Tue Feb 11 18:13:45 2014 +0000
+++ b/distrib/sets/lists/comp/md.amd64 Tue Feb 11 20:17:16 2014 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: md.amd64,v 1.213 2014/02/07 23:18:04 dsl Exp $
+# $NetBSD: md.amd64,v 1.214 2014/02/11 20:17:16 dsl Exp $
./usr/include/amd64 comp-c-include
./usr/include/amd64/ansi.h comp-c-include
@@ -19,7 +19,7 @@
./usr/include/amd64/endian_machdep.h comp-c-include
./usr/include/amd64/fenv.h comp-c-include
./usr/include/amd64/float.h comp-c-include
-./usr/include/amd64/fpu.h comp-c-include
+./usr/include/amd64/fpu.h comp-c-include obsolete
./usr/include/amd64/frame.h comp-c-include
./usr/include/amd64/frame_regs.h comp-c-include
./usr/include/amd64/gdt.h comp-c-include
@@ -431,6 +431,7 @@
./usr/include/x86/cputypes.h comp-c-include
./usr/include/x86/cpuvar.h comp-c-include
./usr/include/x86/float.h comp-c-include
+./usr/include/x86/fpu.h comp-c-include
./usr/include/x86/ieee.h comp-c-include
./usr/include/x86/ieeefp.h comp-c-include
./usr/include/x86/intr.h comp-c-include
diff -r 379104c0dafe -r 0cf020bd62e0 sys/arch/amd64/amd64/fpu.c
--- a/sys/arch/amd64/amd64/fpu.c Tue Feb 11 18:13:45 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,484 +0,0 @@
-/* $NetBSD: fpu.c,v 1.48 2014/02/09 23:02:25 dsl Exp $ */
-
-/*-
- * Copyright (c) 2008 The NetBSD Foundation, Inc. All
- * rights reserved.
- *
- * This code is derived from software developed for The NetBSD Foundation
- * by Andrew Doran.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)npx.c 7.2 (Berkeley) 5/12/91
- */
-
-/*-
- * Copyright (c) 1994, 1995, 1998 Charles M. Hannum. All rights reserved.
- * Copyright (c) 1990 William Jolitz.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)npx.c 7.2 (Berkeley) 5/12/91
- */
-
-/*
- * XXXfvdl update copyright notice. this started out as a stripped isa/npx.c
- */
-
-#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.48 2014/02/09 23:02:25 dsl Exp $");
-
-#include "opt_multiprocessor.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/conf.h>
-#include <sys/cpu.h>
-#include <sys/file.h>
-#include <sys/proc.h>
-#include <sys/kernel.h>
-
-#include <machine/cpu.h>
-#include <machine/intr.h>
-#include <machine/cpufunc.h>
-#include <machine/pcb.h>
-#include <machine/trap.h>
-#include <machine/specialreg.h>
-#include <machine/fpu.h>
-
-#ifdef XEN
-#define clts() HYPERVISOR_fpu_taskswitch(0)
-#define stts() HYPERVISOR_fpu_taskswitch(1)
-#endif
-
-/*
- * We do lazy initialization and switching using the TS bit in cr0 and the
- * MDL_USEDFPU bit in mdlwp.
- *
- * DNA exceptions are handled like this:
- *
- * 1) If there is no FPU, return and go to the emulator.
- * 2) If someone else has used the FPU, save its state into that lwp's PCB.
- * 3a) If MDL_USEDFPU is not set, set it and initialize the FPU.
- * 3b) Otherwise, reload the lwp's previous FPU state.
- *
- * When a lwp is created or exec()s, its saved cr0 image has the TS bit
- * set and the MDL_USEDFPU bit clear. The MDL_USEDFPU bit is set when the
- * lwp first gets a DNA and the FPU is initialized. The TS bit is turned
- * off when the FPU is used, and turned on again later when the lwp's FPU
- * state is saved.
- */
-
-void fpudna(struct cpu_info *);
-
-/*
- * The following table is used to ensure that the FPE_... value
- * that is passed as a trapcode to the signal handler of the user
- * process does not have more than one bit set.
- *
- * Multiple bits may be set if SSE simd instructions generate errors
- * on more than one value or if the user process modifies the control
- * word while a status word bit is already set (which this is a sign
- * of bad coding).
- * We have no choise than to narrow them down to one bit, since we must
- * not send a trapcode that is not exactly one of the FPE_ macros.
- *
- * The mechanism has a static table with 127 entries. Each combination
- * of the 7 FPU status word exception bits directly translates to a
- * position in this table, where a single FPE_... value is stored.
- * This FPE_... value stored there is considered the "most important"
- * of the exception bits and will be sent as the signal code. The
- * precedence of the bits is based upon Intel Document "Numerical
- * Applications", Chapter "Special Computational Situations".
- *
- * The code to choose one of these values does these steps:
- * 1) Throw away status word bits that cannot be masked.
- * 2) Throw away the bits currently masked in the control word,
- * assuming the user isn't interested in them anymore.
- * 3) Reinsert status word bit 7 (stack fault) if it is set, which
- * cannot be masked but must be presered.
- * 'Stack fault' is a sub-class of 'invalid operation'.
- * 4) Use the remaining bits to point into the trapcode table.
- *
- * The 6 maskable bits in order of their preference, as stated in the
- * above referenced Intel manual:
- * 1 Invalid operation (FP_X_INV)
- * 1a Stack underflow
- * 1b Stack overflow
- * 1c Operand of unsupported format
- * 1d SNaN operand.
- * 2 QNaN operand (not an exception, irrelavant here)
- * 3 Any other invalid-operation not mentioned above or zero divide
- * (FP_X_INV, FP_X_DZ)
- * 4 Denormal operand (FP_X_DNML)
- * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
- * 6 Inexact result (FP_X_IMP)
- *
- * NB: the above seems to mix up the mxscr error bits and the x87 ones.
- * They are in the same order, but there is no EN_SW_STACK_FAULT in the mmx
- * status.
- *
- * The table is nearly, but not quite, in bit order (ZERODIV and DENORM
- * are swapped).
- *
- * This table assumes that any stack fault is cleared - so that an INVOP
- * fault will only be reported as FLTSUB once.
- * This might not happen if the mask is being changed.
- */
-#define FPE_xxx1(f) (f & EN_SW_INVOP \
- ? (f & EN_SW_STACK_FAULT ? FPE_FLTSUB : FPE_FLTINV) \
- : f & EN_SW_ZERODIV ? FPE_FLTDIV \
- : f & EN_SW_DENORM ? FPE_FLTUND \
- : f & EN_SW_OVERFLOW ? FPE_FLTOVF \
- : f & EN_SW_UNDERFLOW ? FPE_FLTUND \
- : f & EN_SW_PRECLOSS ? FPE_FLTRES \
- : f & EN_SW_STACK_FAULT ? FPE_FLTSUB : 0)
-#define FPE_xxx2(f) FPE_xxx1(f), FPE_xxx1((f + 1))
-#define FPE_xxx4(f) FPE_xxx2(f), FPE_xxx2((f + 2))
-#define FPE_xxx8(f) FPE_xxx4(f), FPE_xxx4((f + 4))
-#define FPE_xxx16(f) FPE_xxx8(f), FPE_xxx8((f + 8))
-#define FPE_xxx32(f) FPE_xxx16(f), FPE_xxx16((f + 16))
-static const uint8_t fpetable[128] = {
- FPE_xxx32(0), FPE_xxx32(32), FPE_xxx32(64), FPE_xxx32(96)
-};
-#undef FPE_xxx1
-#undef FPE_xxx2
-#undef FPE_xxx4
-#undef FPE_xxx8
-#undef FPE_xxx16
-#undef FPE_xxx32
-
-/*
- * Init the FPU.
- */
-void
-fpuinit(struct cpu_info *ci)
-{
- clts();
- fninit();
- stts();
-}
-
-/*
- * This is a synchronous trap on either an x87 instruction (due to an
- * unmasked error on the previous x87 instruction) or on an SSE/SSE2 etc
- * instruction due to an error on the instruction itself.
- *
- * If trap actually generates a signal, then the fpu state is saved
- * and then copied onto the process's user-stack, and then recovered
- * from there when the signal returns (or from the jmp_buf if the
- * signal handler exits with a longjmp()).
- *
- * All this code need to do is save the reason for the trap.
- * For x87 interrupts the status word bits need clearing to stop the
- * trap re-occurring.
- *
- * The mxcsr bits are 'sticky' and need clearing to not confuse a later trap.
- *
- * Since this is a synchronous trap, the fpu registers must still belong
- * to the correct process (we trap through an interrupt gate so that
- * interrupts are disabled on entry).
- * Interrupts (these better include IPIs) are left disabled until we've
- * finished looking at fpu registers.
- *
- * For amd64 the calling code (in amd64_trap.S) has already checked
- * that we trapped from usermode.
- */
-
-void
-fputrap(struct trapframe *frame)
-{
- uint32_t statbits;
- ksiginfo_t ksi;
-
- /*
- * At this point, fpcurlwp should be curlwp. If it wasn't, the TS bit
- * should be set, and we should have gotten a DNA exception.
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