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[src/trunk]: src/sys/arch Support to check the clock gating for Armada XP in ...



details:   https://anonhg.NetBSD.org/src/rev/cad36080561d
branches:  trunk
changeset: 325404:cad36080561d
user:      kiyohara <kiyohara%NetBSD.org@localhost>
date:      Mon Dec 23 04:12:09 2013 +0000

description:
Support to check the clock gating for Armada XP in armadaxp.c.
Also move the checking for clock gate of Kirkwood into kirkwood.c.

diffstat:

 sys/arch/arm/marvell/armadaxp.c             |  54 +++++++++++++++++++++++++-
 sys/arch/arm/marvell/kirkwood.c             |  44 ++++++++++++++++++++-
 sys/arch/arm/marvell/mvsoc.c                |  60 ++++++++++------------------
 sys/arch/arm/marvell/mvsocreg.h             |   6 ++-
 sys/arch/arm/marvell/mvsocvar.h             |   6 ++-
 sys/arch/evbarm/armadaxp/armadaxp_machdep.c |   5 +-
 sys/arch/evbarm/marvell/marvell_machdep.c   |   6 +-
 7 files changed, 133 insertions(+), 48 deletions(-)

diffs (truncated from 411 to 300 lines):

diff -r 0813814f8d4b -r cad36080561d sys/arch/arm/marvell/armadaxp.c
--- a/sys/arch/arm/marvell/armadaxp.c   Mon Dec 23 03:19:43 2013 +0000
+++ b/sys/arch/arm/marvell/armadaxp.c   Mon Dec 23 04:12:09 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armadaxp.c,v 1.5 2013/12/23 03:19:43 kiyohara Exp $    */
+/*     $NetBSD: armadaxp.c,v 1.6 2013/12/23 04:12:09 kiyohara Exp $    */
 /*******************************************************************************
 Copyright (C) Marvell International Ltd. and its affiliates
 
@@ -37,7 +37,7 @@
 *******************************************************************************/
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.5 2013/12/23 03:19:43 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.6 2013/12/23 04:12:09 kiyohara Exp $");
 
 #define _INTR_PRIVATE
 
@@ -149,6 +149,37 @@
        .pic_name = "armadaxp",
 };
 
+static struct {
+       bus_size_t offset;
+       uint32_t bits;
+} clkgatings[]= {
+       { ARMADAXP_GBE3_BASE,   (1 << 1) },
+       { ARMADAXP_GBE2_BASE,   (1 << 2) },
+       { ARMADAXP_GBE1_BASE,   (1 << 3) },
+       { ARMADAXP_GBE0_BASE,   (1 << 4) },
+       { MVSOC_PEX_BASE,       (1 << 5) },
+       { ARMADAXP_PEX01_BASE,  (1 << 6) },
+       { ARMADAXP_PEX02_BASE,  (1 << 7) },
+       { ARMADAXP_PEX03_BASE,  (1 << 8) },
+       { ARMADAXP_PEX10_BASE,  (1 << 9) },
+       { ARMADAXP_PEX11_BASE,  (1 << 10) },
+       { ARMADAXP_PEX12_BASE,  (1 << 11) },
+       { ARMADAXP_PEX13_BASE,  (1 << 12) },
+#if 0
+       { NetA, (1 << 13) },
+#endif
+       { ARMADAXP_SATAHC_BASE, (1 << 14) | (1 << 15) | (1 << 29) | (1 << 30) },
+       { ARMADAXP_LCD_BASE,    (1 << 16) },
+       { ARMADAXP_SDIO_BASE,   (1 << 17) },
+       { ARMADAXP_USB1_BASE,   (1 << 19) },
+       { ARMADAXP_USB2_BASE,   (1 << 20) },
+       { ARMADAXP_PEX2_BASE,   (1 << 26) },
+       { ARMADAXP_PEX3_BASE,   (1 << 27) },
+#if 0
+       { DDR, (1 << 28) },
+#endif
+};
+
 /*
  * armadaxp_intr_bootstrap:
  *
@@ -420,3 +451,22 @@
        /* Mark as enabled */
        iocc_state = 1;
 }
+
+int     
+armadaxp_clkgating(struct marvell_attach_args *mva)
+{
+       uint32_t val;
+       int i;
+
+       for (i = 0; i < __arraycount(clkgatings); i++) {
+               if (clkgatings[i].offset == mva->mva_offset) {
+                       val = read_miscreg(ARMADAXP_MISC_PMCGC);
+                       if ((val & clkgatings[i].bits) == clkgatings[i].bits)
+                               /* Clock enabled */
+                               return 0; 
+                       return 1;
+               }
+       } 
+       /* Clock Gating not support */
+       return 0;
+}
diff -r 0813814f8d4b -r cad36080561d sys/arch/arm/marvell/kirkwood.c
--- a/sys/arch/arm/marvell/kirkwood.c   Mon Dec 23 03:19:43 2013 +0000
+++ b/sys/arch/arm/marvell/kirkwood.c   Mon Dec 23 04:12:09 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: kirkwood.c,v 1.7 2012/09/06 03:05:41 msaitoh Exp $     */
+/*     $NetBSD: kirkwood.c,v 1.8 2013/12/23 04:12:09 kiyohara Exp $    */
 /*
  * Copyright (c) 2010 KIYOHARA Takashi
  * All rights reserved.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: kirkwood.c,v 1.7 2012/09/06 03:05:41 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: kirkwood.c,v 1.8 2013/12/23 04:12:09 kiyohara Exp $");
 
 #define _INTR_PRIVATE
 
@@ -88,6 +88,27 @@
        .pic_name = "kirkwood",
 };
 
+static struct {
+       bus_size_t offset;
+       uint32_t bits;
+} clkgatings[]= {
+       { KIRKWOOD_GBE0_BASE,   (1 << 0) },
+       { MVSOC_PEX_BASE,       (1 << 2) },
+       { KIRKWOOD_USB_BASE,    (1 << 3) },
+       { KIRKWOOD_SDIO_BASE,   (1 << 4) },
+       { KIRKWOOD_MTS_BASE,    (1 << 5) },
+#if 0
+       { Dunit, (1 << 6) },    /* SDRAM Unit Clock */
+       { Runit, (1 << 7) },    /* Runit Clock */
+#endif
+       { KIRKWOOD_IDMAC_BASE,  (1 << 8) | (1 << 16) },
+       { KIRKWOOD_AUDIO_BASE,  (1 << 9) },
+       { KIRKWOOD_SATAHC_BASE, (1 << 14) | (1 << 15) },
+       { KIRKWOOD_CESA_BASE,   (1 << 17) },
+       { KIRKWOOD_GBE1_BASE,   (1 << 19) },
+       { KIRKWOOD_TDM_BASE,    (1 << 20) },
+};
+
 
 /*
  * kirkwood_intr_bootstrap:
@@ -260,3 +281,22 @@
 #undef MHz
 
 }
+
+int
+kirkwood_clkgating(struct marvell_attach_args *mva)
+{
+       uint32_t val;
+       int i;
+
+       for (i = 0; i < __arraycount(clkgatings); i++) {
+               if (clkgatings[i].offset == mva->mva_offset) {
+                       val = read_mlmbreg(MVSOC_MLMB_CLKGATING);
+                       if ((val & clkgatings[i].bits) == clkgatings[i].bits)
+                               /* Clock enabled */
+                               return 0;
+                       return 1;
+               }
+       }
+       /* Clock Gating not support */
+       return 0;
+}
diff -r 0813814f8d4b -r cad36080561d sys/arch/arm/marvell/mvsoc.c
--- a/sys/arch/arm/marvell/mvsoc.c      Mon Dec 23 03:19:43 2013 +0000
+++ b/sys/arch/arm/marvell/mvsoc.c      Mon Dec 23 04:12:09 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsoc.c,v 1.15 2013/12/23 03:19:43 kiyohara Exp $      */
+/*     $NetBSD: mvsoc.c,v 1.16 2013/12/23 04:12:09 kiyohara Exp $      */
 /*
  * Copyright (c) 2007, 2008 KIYOHARA Takashi
  * All rights reserved.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.15 2013/12/23 03:19:43 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.16 2013/12/23 04:12:09 kiyohara Exp $");
 
 #include "opt_cputypes.h"
 #include "opt_mvsoc.h"
@@ -70,6 +70,7 @@
 vaddr_t mlmb_base;
 
 void (*mvsoc_intr_init)(void);
+int (*mvsoc_clkgating)(struct marvell_attach_args *);
 
 
 #ifdef MVSOC_CONSOLE_EARLY
@@ -345,7 +346,6 @@
        int unit;
        bus_size_t offset;
        int irq;
-       uint32_t clkpwr_bit;
 } mvsoc_periphs[] = {
 #if defined(ORION)
 #define ORION_IRQ_TMR          (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ)
@@ -490,23 +490,15 @@
     { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
     { KIRKWOOD(88F6281),"com",     0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT },
     { KIRKWOOD(88F6281),"com",     1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT },
-    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT,
-                                       MVSOC_MLMB_CLKGATING_BIT(3) },
+    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT },
     { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT },
     { KIRKWOOD(88F6281),"gttwsi",  0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI },
-    { KIRKWOOD(88F6281),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT,
-                                       MVSOC_MLMB_CLKGATING_BIT(17) },
-    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT,
-                                       MVSOC_MLMB_CLKGATING_BIT(0) },
-    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT,
-                                       MVSOC_MLMB_CLKGATING_BIT(19) },
-    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,  KIRKWOOD_IRQ_PEX0INT,
-                                       MVSOC_MLMB_CLKGATING_BIT(2) },
-    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA,
-                                       MVSOC_MLMB_CLKGATING_BIT(14) |
-                                       MVSOC_MLMB_CLKGATING_BIT(15) },
-    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT,
-                                       MVSOC_MLMB_CLKGATING_BIT(4) },
+    { KIRKWOOD(88F6281),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT },
+    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,  KIRKWOOD_IRQ_PEX0INT },
+    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA },
+    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
 
     { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE,  KIRKWOOD_IRQ_TMR },
     { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE,  KIRKWOOD_IRQ_GPIOLO7_0},
@@ -561,7 +553,7 @@
     { ARMADAXP(MV78130), "com",    1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 },
     { ARMADAXP(MV78130), "com",    2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 },
     { ARMADAXP(MV78130), "com",    3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 },
-    { ARMADAXP(MV78130), "mvsocrtc",0, ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
+    { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
     { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 },
     { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 },
     { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT },
@@ -587,7 +579,7 @@
     { ARMADAXP(MV78160), "com",    1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 },
     { ARMADAXP(MV78160), "com",    2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 },
     { ARMADAXP(MV78160), "com",    3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 },
-    { ARMADAXP(MV78160), "mvsocrtc",0, ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
+    { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
     { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 },
     { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 },
     { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT },
@@ -615,7 +607,7 @@
     { ARMADAXP(MV78230), "com",    1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 },
     { ARMADAXP(MV78230), "com",    2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 },
     { ARMADAXP(MV78230), "com",    3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 },
-    { ARMADAXP(MV78230), "mvsocrtc",0, ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
+    { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
     { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 },
     { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 },
     { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT },
@@ -642,7 +634,7 @@
     { ARMADAXP(MV78260), "com",    1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 },
     { ARMADAXP(MV78260), "com",    2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 },
     { ARMADAXP(MV78260), "com",    3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 },
-    { ARMADAXP(MV78260), "mvsocrtc",0, ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
+    { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
     { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 },
     { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 },
     { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT },
@@ -670,7 +662,7 @@
     { ARMADAXP(MV78460), "com",    1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 },
     { ARMADAXP(MV78460), "com",    2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 },
     { ARMADAXP(MV78460), "com",    3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 },
-    { ARMADAXP(MV78460), "mvsocrtc",0, ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
+    { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
     { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 },
     { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 },
     { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT },
@@ -716,7 +708,6 @@
        struct marvell_attach_args mva;
        uint16_t model;
        uint8_t rev;
-       uint32_t clkpwr, clkpwrbit;
        int i;
 
        sc->sc_dev = self;
@@ -756,20 +747,6 @@
                if (mvsoc_periphs[i].model != model)
                        continue;
 
-               /* Skip clock disabled devices */
-               clkpwrbit = mvsoc_periphs[i].clkpwr_bit;
-               if (clkpwrbit != 0) {
-                       clkpwr = read_mlmbreg(MVSOC_MLMB_CLKGATING);
-
-                       if ((clkpwr & clkpwrbit) == 0) {
-                               aprint_normal("%s: %s%d clock disabled\n",
-                                   device_xname(self),
-                                   mvsoc_periphs[i].name,
-                                   mvsoc_periphs[i].unit);
-                               continue;
-                       }
-               }
-
                mva.mva_name = mvsoc_periphs[i].name;
                mva.mva_model = model;
                mva.mva_revision = rev;
@@ -782,6 +759,13 @@
                mva.mva_dmat = sc->sc_dmat;
                mva.mva_irq = mvsoc_periphs[i].irq;
 
+               /* Skip clock disabled devices */
+               if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) {
+                       aprint_normal_dev(self, "%s%d clock disabled\n",
+                           mvsoc_periphs[i].name, mvsoc_periphs[i].unit);
+                       continue;
+               }
+
                config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva,
                    mvsoc_print, mvsoc_search);



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