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[src/trunk]: src/sys/arch/aarch64 fix build with aarch64 gcc/gas



details:   https://anonhg.NetBSD.org/src/rev/71ab243a9304
branches:  trunk
changeset: 324741:71ab243a9304
user:      ryo <ryo%NetBSD.org@localhost>
date:      Tue Jul 17 10:01:59 2018 +0000

description:
fix build with aarch64 gcc/gas

diffstat:

 sys/arch/aarch64/aarch64/copyinout.S |   6 ++-
 sys/arch/aarch64/aarch64/cpuswitch.S |   6 ++-
 sys/arch/aarch64/aarch64/fusu.S      |   7 +++-
 sys/arch/aarch64/aarch64/genassym.cf |  58 +++++++++++++++++++++++++++++++++++-
 sys/arch/aarch64/aarch64/locore.S    |  16 +++++----
 sys/arch/aarch64/aarch64/vectors.S   |   4 +-
 sys/arch/aarch64/include/pte.h       |   6 +++-
 7 files changed, 86 insertions(+), 17 deletions(-)

diffs (225 lines):

diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/aarch64/copyinout.S
--- a/sys/arch/aarch64/aarch64/copyinout.S      Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/aarch64/copyinout.S      Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: copyinout.S,v 1.3 2018/04/01 04:35:03 ryo Exp $ */
+/* $NetBSD: copyinout.S,v 1.4 2018/07/17 10:01:59 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,8 +32,10 @@
 #include <aarch64/asm.h>
 #include "assym.h"
 
-RCSID("$NetBSD: copyinout.S,v 1.3 2018/04/01 04:35:03 ryo Exp $");
+RCSID("$NetBSD: copyinout.S,v 1.4 2018/07/17 10:01:59 ryo Exp $");
 
+#define fp     x29
+#define lr     x30
 
        .macro enter_cpu_onfault
        stp     fp, lr, [sp, #-16]!     /* save fp, lr */
diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/aarch64/cpuswitch.S
--- a/sys/arch/aarch64/aarch64/cpuswitch.S      Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/aarch64/cpuswitch.S      Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.2 2018/07/09 06:11:12 ryo Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.3 2018/07/17 10:01:59 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -35,7 +35,9 @@
 
 #include "opt_ddb.h"
 
-RCSID("$NetBSD: cpuswitch.S,v 1.2 2018/07/09 06:11:12 ryo Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.3 2018/07/17 10:01:59 ryo Exp $")
+
+#define lr     x30
 
 /*
  * At IPL_SCHED:
diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/aarch64/fusu.S
--- a/sys/arch/aarch64/aarch64/fusu.S   Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/aarch64/fusu.S   Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fusu.S,v 1.3 2018/04/01 04:35:03 ryo Exp $     */
+/*     $NetBSD: fusu.S,v 1.4 2018/07/17 10:01:59 ryo Exp $     */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,7 +32,10 @@
 #include <aarch64/asm.h>
 #include "assym.h"
 
-RCSID("$NetBSD: fusu.S,v 1.3 2018/04/01 04:35:03 ryo Exp $");
+RCSID("$NetBSD: fusu.S,v 1.4 2018/07/17 10:01:59 ryo Exp $");
+
+#define fp     x29
+#define lr     x30
 
        .macro enter_cpu_onfault
        stp     fp, lr, [sp, #-16]!     /* save fp, lr */
diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/aarch64/genassym.cf
--- a/sys/arch/aarch64/aarch64/genassym.cf      Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/aarch64/genassym.cf      Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.4 2018/07/10 08:35:58 ryo Exp $
+# $NetBSD: genassym.cf,v 1.5 2018/07/17 10:01:59 ryo Exp $
 #-
 # Copyright (c) 2014 The NetBSD Foundation, Inc.
 # All rights reserved.
@@ -50,6 +50,7 @@
 include <aarch64/vmparam.h>
 include <aarch64/frame.h>
 include <aarch64/armreg.h>
+include <aarch64/pte.h>
 
 if defined(_KERNEL_OPT)
 include "opt_multiprocessor.h"
@@ -102,6 +103,61 @@
 #define        L2_C                    L2_C
 #define        L2_AP_KRW               L2_AP(AP_KRW)
 
+define L0_ADDR_BITS            L0_ADDR_BITS
+define L0_SHIFT                L0_SHIFT
+define L0_TABLE                L0_TABLE
+define L1_ADDR_BITS            L1_ADDR_BITS
+define L1_BLOCK                L1_BLOCK
+define L1_SHIFT                L1_SHIFT
+define L1_SIZE                 L1_SIZE
+define L1_TABLE                L1_TABLE
+define L2_ADDR_BITS            L2_ADDR_BITS
+define L2_BLK_OA               L2_BLK_OA
+define L2_BLOCK                L2_BLOCK
+define L2_BLOCK_MASK           L2_BLOCK_MASK
+define L2_SHIFT                L2_SHIFT
+define L2_SIZE                 L2_SIZE
+define LX_BLKPAG_UXN           LX_BLKPAG_UXN
+define LX_BLKPAG_PXN           LX_BLKPAG_PXN
+define LX_BLKPAG_AF            LX_BLKPAG_AF
+define LX_BLKPAG_AP_RW         LX_BLKPAG_AP_RW
+define LX_BLKPAG_SH_IS         LX_BLKPAG_SH_IS
+define LX_BLKPAG_ATTR_INDX_0   LX_BLKPAG_ATTR_INDX_0
+define LX_BLKPAG_ATTR_INDX_1   LX_BLKPAG_ATTR_INDX_1
+define LX_BLKPAG_ATTR_INDX_2   LX_BLKPAG_ATTR_INDX_2
+define LX_BLKPAG_ATTR_INDX_3   LX_BLKPAG_ATTR_INDX_3
+define Ln_ENTRIES              Ln_ENTRIES
+
+define TCR_AS64K               TCR_AS64K
+define TCR_TG1_16KB            TCR_TG1_16KB
+define TCR_TG1_4KB             TCR_TG1_4KB
+define TCR_TG1_64KB            TCR_TG1_64KB
+define TCR_TG0_16KB            TCR_TG0_16KB
+define TCR_TG0_4KB             TCR_TG0_4KB
+define TCR_TG0_64KB            TCR_TG0_64KB
+define TCR_SH1_OUTER           TCR_SH1_OUTER
+define TCR_SH1_INNER           TCR_SH1_INNER
+define TCR_ORGN1_NC            TCR_ORGN1_NC
+define TCR_ORGN1_WB_WA         TCR_ORGN1_WB_WA
+define TCR_ORGN1_WT            TCR_ORGN1_WT
+define TCR_ORGN1_WB            TCR_ORGN1_WB
+define TCR_IRGN1_NC            TCR_IRGN1_NC
+define TCR_IRGN1_WB_WA         TCR_IRGN1_WB_WA
+define TCR_IRGN1_WT            TCR_IRGN1_WT
+define TCR_IRGN1_WB            TCR_IRGN1_WB
+define TCR_T1SZ                TCR_T1SZ
+define TCR_SH0_OUTER           TCR_SH0_OUTER
+define TCR_SH0_INNER           TCR_SH0_INNER
+define TCR_ORGN0_NC            TCR_ORGN0_NC
+define TCR_ORGN0_WB_WA         TCR_ORGN0_WB_WA
+define TCR_ORGN0_WT            TCR_ORGN0_WT
+define TCR_ORGN0_WB            TCR_ORGN0_WB
+define TCR_IRGN0_NC            TCR_IRGN0_NC
+define TCR_IRGN0_WB_WA         TCR_IRGN0_WB_WA
+define TCR_IRGN0_WT            TCR_IRGN0_WT
+define TCR_IRGN0_WB            TCR_IRGN0_WB
+define TCR_T0SZ                TCR_T0SZ
+
 define EFAULT                  EFAULT
 
 define PAGE_SIZE               PAGE_SIZE
diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/aarch64/locore.S
--- a/sys/arch/aarch64/aarch64/locore.S Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/aarch64/locore.S Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.11 2018/07/17 00:32:28 christos Exp $     */
+/*     $NetBSD: locore.S,v 1.12 2018/07/17 10:01:59 ryo Exp $  */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -33,10 +33,9 @@
 
 #include <aarch64/asm.h>
 #include <aarch64/hypervisor.h>
-#include <aarch64/pte.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.11 2018/07/17 00:32:28 christos Exp $")
+RCSID("$NetBSD: locore.S,v 1.12 2018/07/17 10:01:59 ryo Exp $")
 
 /* #define DEBUG_LOCORE */
 /* #define DEBUG_MMU */
@@ -48,10 +47,10 @@
 #define LOCORE_EL2
 
 /* attributes are defined in MAIR_EL1 */
-#define L2_BLKPAG_ATTR_NORMAL_WB       __SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
-#define L2_BLKPAG_ATTR_NORMAL_NC       __SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
-#define L2_BLKPAG_ATTR_NORMAL_WT       __SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
-#define L2_BLKPAG_ATTR_DEVICE_MEM      __SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
+#define L2_BLKPAG_ATTR_NORMAL_WB       LX_BLKPAG_ATTR_INDX_0
+#define L2_BLKPAG_ATTR_NORMAL_NC       LX_BLKPAG_ATTR_INDX_1
+#define L2_BLKPAG_ATTR_NORMAL_WT       LX_BLKPAG_ATTR_INDX_2
+#define L2_BLKPAG_ATTR_DEVICE_MEM      LX_BLKPAG_ATTR_INDX_3
 
 #define PRINT(string)  bl xprint;.asciz string;.align 2
 
@@ -61,6 +60,9 @@
 #define VERBOSE(string)
 #endif
 
+#define fp     x29
+#define lr     x30
+
 /* load far effective address (pc relative) */
 .macro ADDR, reg, addr
        adrp    \reg, \addr
diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/aarch64/vectors.S
--- a/sys/arch/aarch64/aarch64/vectors.S        Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/aarch64/vectors.S        Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: vectors.S,v 1.5 2018/04/01 04:35:03 ryo Exp $  */
+/*     $NetBSD: vectors.S,v 1.6 2018/07/17 10:01:59 ryo Exp $  */
 
 #include <aarch64/asm.h>
 #include "assym.h"
@@ -67,7 +67,7 @@
        str     x0, [x1, #L_PRIVATE]    /* curlwp->l_private = tpidr_el0 */
        .endif
 
-       adr     lr, el\el\()_trap_exit  /* el[01]_trap_exit */
+       adr     x30, el\el\()_trap_exit /* el[01]_trap_exit */
        mov     x0, sp
        b       \label
        .endm
diff -r 70bd7141d6d1 -r 71ab243a9304 sys/arch/aarch64/include/pte.h
--- a/sys/arch/aarch64/include/pte.h    Tue Jul 17 09:58:14 2018 +0000
+++ b/sys/arch/aarch64/include/pte.h    Tue Jul 17 10:01:59 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.3 2018/04/01 04:35:03 ryo Exp $ */
+/* $NetBSD: pte.h,v 1.4 2018/07/17 10:01:59 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -72,6 +72,10 @@
 #define LX_BLKPAG_APUSER       __BIT(6)
 #define LX_BLKPAG_NS           __BIT(5)
 #define LX_BLKPAG_ATTR_INDX    __BITS(4,2)     /* refer MAIR_EL1 attr<n> */
+#define  LX_BLKPAG_ATTR_INDX_0 __SHIFTIN(0,LX_BLKPAG_ATTR_INDX)
+#define  LX_BLKPAG_ATTR_INDX_1 __SHIFTIN(1,LX_BLKPAG_ATTR_INDX)
+#define  LX_BLKPAG_ATTR_INDX_2 __SHIFTIN(2,LX_BLKPAG_ATTR_INDX)
+#define  LX_BLKPAG_ATTR_INDX_3 __SHIFTIN(3,LX_BLKPAG_ATTR_INDX)
 #define LX_TYPE                        __BIT(1)
 #define LX_TYPE_BLK            __SHIFTIN(0, LX_TYPE)
 #define LX_TYPE_TBL            __SHIFTIN(1, LX_TYPE)



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