[src/trunk]: src/sys/arch/x86/x86 Add XXX in fpuinit_mxcsr_mask.

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9ef71ef759dd
branches:  trunk
changeset: 323625:9ef71ef759dd
user:      maxv <maxv%NetBSD.org@localhost>
date:      Sat Jun 23 10:06:02 2018 +0000

description:
Add XXX in fpuinit_mxcsr_mask.

diffstat:

 sys/arch/x86/x86/fpu.c |  9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diffs (30 lines):

diff -r f1372b6492da -r 9ef71ef759dd sys/arch/x86/x86/fpu.c
--- a/sys/arch/x86/x86/fpu.c    Sat Jun 23 10:02:39 2018 +0000
+++ b/sys/arch/x86/x86/fpu.c    Sat Jun 23 10:06:02 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu.c,v 1.42 2018/06/22 06:22:37 maxv Exp $    */
+/*     $NetBSD: fpu.c,v 1.43 2018/06/23 10:06:02 maxv Exp $    */
 
 /*
  * Copyright (c) 2008 The NetBSD Foundation, Inc.  All
@@ -96,7 +96,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.42 2018/06/22 06:22:37 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.43 2018/06/23 10:06:02 maxv Exp $");
 
 #include "opt_multiprocessor.h"
 
@@ -263,6 +263,11 @@
                x86_fpu_mxcsr_mask = fpusave.sv_xmm.fx_mxcsr_mask;
        }
 #else
+       /*
+        * XXX XXX XXX: On Xen the FXSAVE above faults. That's because
+        * &fpusave is not 16-byte aligned. Stack alignment problem
+        * somewhere, it seems.
+        */
        x86_fpu_mxcsr_mask = __INITIAL_MXCSR_MASK__;
 #endif
 }