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[src/trunk]: src/sys/dev/pci Style fix. No functional change.
details: https://anonhg.NetBSD.org/src/rev/2cc6329adb52
branches: trunk
changeset: 323552:2cc6329adb52
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Wed Jun 20 05:19:12 2018 +0000
description:
Style fix. No functional change.
diffstat:
sys/dev/pci/if_wm.c | 268 ++++++++++++++++++++++++---------------------------
1 files changed, 128 insertions(+), 140 deletions(-)
diffs (truncated from 887 to 300 lines):
diff -r afbe5ad63526 -r 2cc6329adb52 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Wed Jun 20 05:01:39 2018 +0000
+++ b/sys/dev/pci/if_wm.c Wed Jun 20 05:19:12 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.581 2018/06/01 08:56:00 maxv Exp $ */
+/* $NetBSD: if_wm.c,v 1.582 2018/06/20 05:19:12 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.581 2018/06/01 08:56:00 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.582 2018/06/20 05:19:12 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -193,7 +193,7 @@
/*
* Transmit descriptor list size. Due to errata, we can only have
* 256 hardware descriptors in the ring on < 82544, but we use 4096
- * on >= 82544. We tell the upper layers that they can queue a lot
+ * on >= 82544. We tell the upper layers that they can queue a lot
* of packets, and we go ahead and manage up to 64 (16 for the i82547)
* of them at a time.
*
@@ -247,13 +247,13 @@
typedef union txdescs {
wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
- nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544];
+ nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544];
} txdescs_t;
typedef union rxdescs {
wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
- ext_rxdesc_t sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
- nq_rxdesc_t sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
+ ext_rxdesc_t sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
+ nq_rxdesc_t sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
} rxdescs_t;
#define WM_CDTXOFF(txq, x) ((txq)->txq_descsize * (x))
@@ -271,9 +271,9 @@
};
/*
- * Software state for receive buffers. Each descriptor gets a
- * 2k (MCLBYTES) buffer and a DMA map. For packets which fill
- * more than one buffer, we chain them together.
+ * Software state for receive buffers. Each descriptor gets a 2k (MCLBYTES)
+ * buffer and a DMA map. For packets which fill more than one buffer, we chain
+ * them together.
*/
struct wm_rxsoft {
struct mbuf *rxs_mbuf; /* head of our mbuf chain */
@@ -333,7 +333,7 @@
int txq_ndesc; /* must be a power of two */
size_t txq_descsize; /* a tx descriptor size */
txdescs_t *txq_descs_u;
- bus_dmamap_t txq_desc_dmamap; /* control data DMA map */
+ bus_dmamap_t txq_desc_dmamap; /* control data DMA map */
bus_dma_segment_t txq_desc_seg; /* control data segment */
int txq_desc_rseg; /* real number of control segment */
#define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr
@@ -547,7 +547,7 @@
/* Event counters. */
struct evcnt sc_ev_linkintr; /* Link interrupts */
- /* WM_T_82542_2_1 only */
+ /* WM_T_82542_2_1 only */
struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */
struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */
struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */
@@ -669,7 +669,7 @@
#endif
static inline void wm_io_write(struct wm_softc *, int, uint32_t);
static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
- uint32_t, uint32_t);
+ uint32_t, uint32_t);
static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
/*
@@ -878,7 +878,7 @@
static int32_t wm_ich8_cycle_init(struct wm_softc *);
static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
- uint32_t *);
+ uint32_t *);
static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
static int32_t wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
@@ -1646,13 +1646,13 @@
if (sc->sc_type == WM_T_82574) {
ext_rxdesc_t *rxd = &rxq->rxq_ext_descs[start];
rxd->erx_data.erxd_addr =
- htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
+ htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
rxd->erx_data.erxd_dd = 0;
} else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
nq_rxdesc_t *rxd = &rxq->rxq_nq_descs[start];
rxd->nqrx_data.nrxd_paddr =
- htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
+ htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
/* Currently, split header is not supported. */
rxd->nqrx_data.nrxd_haddr = 0;
} else {
@@ -1810,7 +1810,7 @@
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
- memtype, 0, &memt, &memh, NULL, &memsize) == 0);
+ memtype, 0, &memt, &memh, NULL, &memsize) == 0);
break;
default:
memh_valid = 0;
@@ -1878,8 +1878,8 @@
pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
/* power up chip */
- if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
- NULL)) && error != EOPNOTSUPP) {
+ if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL))
+ && error != EOPNOTSUPP) {
aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
return;
}
@@ -1936,7 +1936,7 @@
counts[PCI_INTR_TYPE_INTX] = 1;
goto alloc_retry;
}
- } else if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
+ } else if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
wm_adjust_qnum(sc, 0); /* must not use multiqueue */
error = wm_setup_legacy(sc);
if (error) {
@@ -1962,7 +1962,7 @@
* Check the function ID (unit number of the chip).
*/
if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
- || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)
+ || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)
|| (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
|| (sc->sc_type == WM_T_82580)
|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
@@ -1989,7 +1989,7 @@
if (sc->sc_type == WM_T_82547) {
callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS);
callout_setfunc(&sc->sc_txfifo_ch,
- wm_82547_txfifo_stall, sc);
+ wm_82547_txfifo_stall, sc);
aprint_verbose_dev(sc->sc_dev,
"using 82547 Tx FIFO stall work-around\n");
}
@@ -2044,7 +2044,7 @@
512 << bytecnt, 512 << maxb);
pcix_cmd = (pcix_cmd &
~PCIX_CMD_BYTECNT_MASK) |
- (maxb << PCIX_CMD_BYTECNT_SHIFT);
+ (maxb << PCIX_CMD_BYTECNT_SHIFT);
pci_conf_write(pa->pa_pc, pa->pa_tag,
sc->sc_pcixe_capoff + PCIX_CMD,
pcix_cmd);
@@ -2256,8 +2256,8 @@
sc->sc_flashh = sc->sc_sh;
sc->sc_ich8_flash_base = 0;
sc->sc_nvm_wordsize =
- (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
- * NVM_SIZE_MULTIPLIER;
+ (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
+ * NVM_SIZE_MULTIPLIER;
/* It is size in bytes, we want words */
sc->sc_nvm_wordsize /= 2;
/* assume 2 banks */
@@ -2832,7 +2832,7 @@
ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
if_register(ifp);
rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET,
- RND_FLAG_DEFAULT);
+ RND_FLAG_DEFAULT);
#ifdef WM_EVENT_COUNTERS
/* Attach event counters. */
@@ -3049,13 +3049,12 @@
txq->txq_next);
ifp->if_oerrors++;
#ifdef WM_DEBUG
- for (i = txq->txq_sdirty; i != txq->txq_snext ;
+ for (i = txq->txq_sdirty; i != txq->txq_snext;
i = WM_NEXTTXS(txq, i)) {
txs = &txq->txq_soft[i];
printf("txs %d tx %d -> %d\n",
i, txs->txs_firstdesc, txs->txs_lastdesc);
- for (j = txs->txs_firstdesc; ;
- j = WM_NEXTTX(txq, j)) {
+ for (j = txs->txs_firstdesc; ; j = WM_NEXTTX(txq, j)) {
if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
printf("\tdesc %d: 0x%" PRIx64 "\n", j,
txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
@@ -4413,7 +4412,7 @@
txq->txq_fifo_head = 0;
txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
txq->txq_fifo_size =
- (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
+ (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
txq->txq_fifo_stall = 0;
}
break;
@@ -4551,12 +4550,12 @@
/*
* On some chipsets, a reset through a memory-mapped write
* cycle can cause the chip to reset before completing the
- * write cycle. This causes major headache that can be
- * avoided by issuing the reset via indirect register writes
- * through I/O space.
+ * write cycle. This causes major headache that can be avoided
+ * by issuing the reset via indirect register writes through
+ * I/O space.
*
* So, if we successfully mapped the I/O BAR at attach time,
- * use that. Otherwise, try our luck with a memory-mapped
+ * use that. Otherwise, try our luck with a memory-mapped
* reset.
*/
if (sc->sc_flags & WM_F_IOH_VALID)
@@ -5197,7 +5196,7 @@
snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
device_xname(sc->sc_dev));
vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
- IPL_NET, wm_linkintr_msix, sc, intr_xname);
+ IPL_NET, wm_linkintr_msix, sc, intr_xname);
if (vih == NULL) {
aprint_error_dev(sc->sc_dev,
"unable to establish MSI-X(for LINK)%s%s\n",
@@ -5308,7 +5307,7 @@
* the multi queue function with MSI-X.
*/
CSR_WRITE(sc, WMREG_EITR_82574(wmq->wmq_intr_idx),
- wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
+ wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
} else {
KASSERT(wmq->wmq_id == 0);
CSR_WRITE(sc, WMREG_ITR, wmq->wmq_itr);
@@ -5829,12 +5828,12 @@
wm_init_manageability(sc);
/*
- * Set up the receive control register; we actually program
- * the register when we set the receive filter. Use multicast
- * address offset type 0.
+ * Set up the receive control register; we actually program the
+ * register when we set the receive filter. Use multicast address
+ * offset type 0.
*
- * Only the i82544 has the ability to strip the incoming
- * CRC, so we don't enable that feature.
+ * Only the i82544 has the ability to strip the incoming CRC, so we
+ * don't enable that feature.
*/
sc->sc_mchash_type = 0;
sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
@@ -6118,7 +6117,7 @@
* if the Tx FIFO ring buffer, otherwise the chip will croak.
*
* We do this by checking the amount of space before the end
- * of the Tx FIFO buffer. If the packet will not fit, we "stall"
+ * of the Tx FIFO buffer. If the packet will not fit, we "stall"
* the Tx FIFO, wait for all remaining packets to drain, reset
* the internal FIFO pointers to the beginning, and restart
* transmission on the interface.
@@ -6934,7 +6933,7 @@
(hlen + sizeof(struct tcphdr)))) {
/*
* TCP/IP headers are not in the first mbuf; we need
- * to do this the slow and painful way. Let's just
+ * to do this the slow and painful way. Let's just
* hope this doesn't happen very often.
*/
struct tcphdr th;
@@ -7030,7 +7029,7 @@
fields |= WTX_TXSM;
tucs = WTX_TCPIP_TUCSS(offset) |
WTX_TCPIP_TUCSO(offset +
- M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
+ M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
WTX_TCPIP_TUCSE(0) /* rest of packet */;
} else if ((m0->m_pkthdr.csum_flags &
(M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) {
@@ -7038,7 +7037,7 @@
fields |= WTX_TXSM;
tucs = WTX_TCPIP_TUCSS(offset) |
WTX_TCPIP_TUCSO(offset +
- M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
+ M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
WTX_TCPIP_TUCSE(0) /* rest of packet */;
} else {
/* Just initialize it to a valid TCP context. */
@@ -7083,7 +7082,7 @@
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