[src/trunk]: src/sys/arch/x86/x86 Enable eager fpu automatically at boot time...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6bc1449d4441
branches:  trunk
changeset: 323498:6bc1449d4441
user:      maxv <maxv%NetBSD.org@localhost>
date:      Sun Jun 17 07:13:02 2018 +0000

description:
Enable eager fpu automatically at boot time if the cpu is affected. Intel
hasn't published a list of its affected products, but it appears that Xen
was given this information since they have a specific detection code.

We could just unconditionally enable eager; but on x86_32 eager may have
a greater performance cost than lazy, and we don't want to lose
performance on unaffected (and ~old) CPUs running NetBSD/i386.

So use the same code as Xen: take Family 6, and whitelist certain models.

diffstat:

 sys/arch/x86/x86/identcpu.c |  52 +++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 50 insertions(+), 2 deletions(-)

diffs (78 lines):

diff -r 2a2214875a94 -r 6bc1449d4441 sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c       Sun Jun 17 06:03:40 2018 +0000
+++ b/sys/arch/x86/x86/identcpu.c       Sun Jun 17 07:13:02 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: identcpu.c,v 1.71 2018/03/30 19:51:53 maxv Exp $       */
+/*     $NetBSD: identcpu.c,v 1.72 2018/06/17 07:13:02 maxv Exp $       */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.71 2018/03/30 19:51:53 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.72 2018/06/17 07:13:02 maxv Exp $");
 
 #include "opt_xen.h"
 
@@ -719,11 +719,59 @@
 #endif
 }
 
+#ifndef XEN
+static void
+cpu_probe_fpu_leak(struct cpu_info *ci)
+{
+       /*
+        * INTEL-SA-00145. Affected CPUs are from Family 6.
+        */
+       if (cpu_vendor != CPUVENDOR_INTEL) {
+               return;
+       }
+       if (CPUID_TO_FAMILY(ci->ci_signature) != 6) {
+               return;
+       }
+
+       switch (CPUID_TO_MODEL(ci->ci_signature)) {
+       /* Atom CPUs are not vulnerable. */
+       case 0x1c: /* Pineview */
+       case 0x26: /* Lincroft */
+       case 0x27: /* Penwell */
+       case 0x35: /* Cloverview */
+       case 0x36: /* Cedarview */
+       case 0x37: /* Baytrail / Valleyview (Silvermont) */
+       case 0x4d: /* Avaton / Rangely (Silvermont) */
+       case 0x4c: /* Cherrytrail / Brasswell */
+       case 0x4a: /* Merrifield */
+       case 0x5a: /* Moorefield */
+       case 0x5c: /* Goldmont */
+       case 0x5f: /* Denverton */
+       case 0x7a: /* Gemini Lake */
+               break;
+
+       /* Knights CPUs are not vulnerable. */
+       case 0x57: /* Knights Landing */
+       case 0x85: /* Knights Mill */
+               break;
+
+       /* The rest is vulnerable. */
+       default:
+               x86_fpu_eager = true;
+               break;
+       }
+}
+#endif
+
 static void
 cpu_probe_fpu(struct cpu_info *ci)
 {
        u_int descs[4];
 
+#ifndef XEN
+       cpu_probe_fpu_leak(ci);
+#endif
+
        x86_fpu_save = FPU_SAVE_FSAVE;
 
 #ifdef i386 /* amd64 always has fxsave, sse and sse2 */