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[src/trunk]: src/sys/arch/arm/imx Modified CCM register defines.
details: https://anonhg.NetBSD.org/src/rev/d04a1895d309
branches: trunk
changeset: 322917:d04a1895d309
user: hkenken <hkenken%NetBSD.org@localhost>
date: Wed May 23 10:42:05 2018 +0000
description:
Modified CCM register defines.
diffstat:
sys/arch/arm/imx/imx6_ahcisata.c | 6 +-
sys/arch/arm/imx/imx6_ccm.c | 6 +-
sys/arch/arm/imx/imx6_ccmreg.h | 185 +++++++++++++++++++++++++-------------
sys/arch/arm/imx/imx6_pcie.c | 8 +-
sys/arch/arm/imx/imx6_usb.c | 6 +-
sys/arch/arm/imx/imx6_usdhc.c | 12 +-
6 files changed, 140 insertions(+), 83 deletions(-)
diffs (truncated from 416 to 300 lines):
diff -r 8ae7d9ac0e05 -r d04a1895d309 sys/arch/arm/imx/imx6_ahcisata.c
--- a/sys/arch/arm/imx/imx6_ahcisata.c Wed May 23 10:21:43 2018 +0000
+++ b/sys/arch/arm/imx/imx6_ahcisata.c Wed May 23 10:42:05 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_ahcisata.c,v 1.6 2017/11/09 05:57:23 hkenken Exp $ */
+/* $NetBSD: imx6_ahcisata.c,v 1.7 2018/05/23 10:42:05 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.6 2017/11/09 05:57:23 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.7 2018/05/23 10:42:05 hkenken Exp $");
#include "locators.h"
#include "opt_imx.h"
@@ -264,7 +264,7 @@
/* AHCISATA clock enable */
v = imx6_ccm_read(CCM_CCGR5);
- imx6_ccm_write(CCM_CCGR5, v | CCM_CCGR5_100M_CLK_ENABLE(3));
+ imx6_ccm_write(CCM_CCGR5, v | __SHIFTIN(3, CCM_CCGR5_SATA_CLK_ENABLE));
/* PLL power up */
if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
diff -r 8ae7d9ac0e05 -r d04a1895d309 sys/arch/arm/imx/imx6_ccm.c
--- a/sys/arch/arm/imx/imx6_ccm.c Wed May 23 10:21:43 2018 +0000
+++ b/sys/arch/arm/imx/imx6_ccm.c Wed May 23 10:42:05 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_ccm.c,v 1.7 2017/11/09 05:57:23 hkenken Exp $ */
+/* $NetBSD: imx6_ccm.c,v 1.8 2018/05/23 10:42:05 hkenken Exp $ */
/*
* Copyright (c) 2010-2012, 2014 Genetec Corporation. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.7 2017/11/09 05:57:23 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.8 2018/05/23 10:42:05 hkenken Exp $");
#include "opt_imx.h"
#include "opt_imx6clk.h"
@@ -539,7 +539,7 @@
case IMX6CLK_PLL6:
/* XXX: iMX6UL has 2 div. which? */
v = imx6_ccm_analog_read(CCM_ANALOG_PLL_ENET);
- switch (v & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) {
+ switch (v & CCM_ANALOG_PLL_ENET_DIV_SELECT) {
case 0:
freq = 25 * 1000 * 1000;
break;
diff -r 8ae7d9ac0e05 -r d04a1895d309 sys/arch/arm/imx/imx6_ccmreg.h
--- a/sys/arch/arm/imx/imx6_ccmreg.h Wed May 23 10:21:43 2018 +0000
+++ b/sys/arch/arm/imx/imx6_ccmreg.h Wed May 23 10:42:05 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_ccmreg.h,v 1.6 2017/11/09 05:57:23 hkenken Exp $ */
+/* $NetBSD: imx6_ccmreg.h,v 1.7 2018/05/23 10:42:05 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -163,7 +163,6 @@
#define CCM_CHSCCDR_IPU1_DI0_PODF __BITS(5, 3)
#define CCM_CHSCCDR_IPU1_DI0_CLK_SEL __BITS(2, 0)
-
#define CCM_CSCDR2 0x00000038
#define CCM_CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)
#define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL __BITS(17, 15)
@@ -189,65 +188,108 @@
#define CCM_CSCDR3_IPU1_HSP_CLK_SEL __BITS(10, 9)
#define CCM_CCOSR 0x00000060
-#define CCM_CCOSR_CLKO2_EN __BIT(24)
-#define CCM_CCOSR_CLKO2_DIV __BITS(23, 21)
-#define CCM_CCOSR_CLKO2_SEL __BITS(20, 16)
-#define CCM_CCOSR_CLK_OUT_SEL __BIT(8)
-#define CCM_CCOSR_CLKO1_EN __BIT(7)
-#define CCM_CCOSR_CLKO1_DIV __BITS(6, 4)
-#define CCM_CCOSR_CLKO1_SEL __BITS(3, 0)
+#define CCM_CCOSR_CLKO2_EN __BIT(24)
+#define CCM_CCOSR_CLKO2_DIV __BITS(23, 21)
+#define CCM_CCOSR_CLKO2_SEL __BITS(20, 16)
+#define CCM_CCOSR_CLK_OUT_SEL __BIT(8)
+#define CCM_CCOSR_CLKO1_EN __BIT(7)
+#define CCM_CCOSR_CLKO1_DIV __BITS(6, 4)
+#define CCM_CCOSR_CLKO1_SEL __BITS(3, 0)
-#define CCM_CCGR2 0x00000070
-#define CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE(n) __SHIFTIN(n, __BITS(27, 26))
-#define CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE(n) __SHIFTIN(n, __BITS(25, 24))
-#define CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE(n) __SHIFTIN(n, __BITS(23, 22))
-#define CCM_CCGR2_IPMUX3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(21, 20))
-#define CCM_CCGR2_IPMUX2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(19, 18))
-#define CCM_CCGR2_IPMUX1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(17, 16))
-#define CCM_CCGR2_IOMUX_IPT_CLK_IO_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
-#define CCM_CCGR2_IIM_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
-#define CCM_CCGR2_I2C3_SERIAL_CLK_ENABLE(n) __SHIFTIN(n, __BITS(11, 10))
-#define CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE(n) __SHIFTIN(n, __BITS(9, 8))
-#define CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
-#define CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
-#define CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
-#define CCM_CCGR4 0x00000078
-#define CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE(N) __SHIFTIN(n, __BITS(31, 30))
-#define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE(n) __SHIFTIN(n, __BITS(29, 28))
-#define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE(n) __SHIFTIN(n, __BITS(27, 26))
-#define CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE(n) __SHIFTIN(n, __BITS(25, 24))
-#define CCM_CCGR4_PWM4_CLK_ENABLE(n) __SHIFTIN(n, __BITS(23, 22))
-#define CCM_CCGR4_PWM3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(21, 20))
-#define CCM_CCGR4_PWM2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(19, 18))
-#define CCM_CCGR4_PWM1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(17, 16))
-#define CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
-#define CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
-#define CCM_CCGR4_CG5_ENABLE(n) __SHIFTIN(n, __BITS(11, 10))
-#define CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE(n) __SHIFTIN(n, __BITS(9, 8))
-#define CCM_CCGR4_CG3_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
-#define CCM_CCGR4_CG2_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
-#define CCM_CCGR4_CG1_ENABLE(n) __SHIFTIN(n, __BITS(3, 2))
-#define CCM_CCGR4_125M_ROOT_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
+#define CCM_CCGR0 0x00000068
+#define CCM_CCGR0_DTCP_CLK_ENABLE __BITS(29, 28)
+#define CCM_CCGR0_DCIC2_CLK_ENABLE __BITS(27, 26)
+#define CCM_CCGR0_DCIC1_CLK_ENABLE __BITS(25, 24)
+#define CCM_CCGR0_ARM_DBG_CLK_ENABLE __BITS(23, 22)
+#define CCM_CCGR0_CAN2_SERIAL_CLK_ENABLE __BITS(21, 20)
+#define CCM_CCGR0_CAN2_CLK_ENABLE __BITS(19, 18)
+#define CCM_CCGR0_CAN1_SERIAL_CLK_ENABLE __BITS(17, 16)
+#define CCM_CCGR0_CAN1_CLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR0_CAAM_WRAPPER_IPG_ENABLE __BITS(13, 12)
+#define CCM_CCGR0_CAAM_WRAPPER_ACLK_ENABLE __BITS(11, 10)
+#define CCM_CCGR0_CAAM_SECURE_MEM_CLK_ENABLE __BITS(9, 8)
+#define CCM_CCGR0_ASRC_CLK_ENABLE __BITS(7, 6)
+#define CCM_CCGR0_APBHDMA_HCLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR0_AIPS_TZ2_CLK_ENABLE __BITS(3, 2)
+#define CCM_CCGR0_AIPS_TZ1_CLK_ENABLE __BITS(1, 0)
+#define CCM_CCGR1 0x0000006C
+#define CCM_CCGR1_GPU3D_CLK_ENABLE __BITS(27, 26)
+#define CCM_CCGR1_GPU2D_CLK_ENABLE __BITS(25, 24)
+#define CCM_CCGR1_GPT_SERIAL_CLK_ENABLE __BITS(23, 22)
+#define CCM_CCGR1_GPT_CLK_ENABLE __BITS(21, 20)
+#define CCM_CCGR1_ESAI_CLK_ENABLE __BITS(17, 16)
+#define CCM_CCGR1_EPIT2_CLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR1_EPIT1_CLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR1_ENET_CLK_ENABLE __BITS(11, 10)
+#define CCM_CCGR1_I2C4_CLK_ENABLE __BITS(9, 8) /* i.MX6DL */
+#define CCM_CCGR1_ECSPI5_CLK_ENABLE __BITS(9, 8) /* i.MX6Q */
+#define CCM_CCGR1_ECSPI4_CLK_ENABLE __BITS(7, 6)
+#define CCM_CCGR1_ECSPI3_CLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR1_ECSPI2_CLK_ENABLE __BITS(3, 2)
+#define CCM_CCGR1_ECSPI1_CLK_ENABLE __BITS(1, 0)
+#define CCM_CCGR2 0x00000070
+#define CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE __BITS(27, 26)
+#define CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE __BITS(25, 24)
+#define CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE __BITS(23, 22)
+#define CCM_CCGR2_IPMUX3_CLK_ENABLE __BITS(21, 20)
+#define CCM_CCGR2_IPMUX2_CLK_ENABLE __BITS(19, 18)
+#define CCM_CCGR2_IPMUX1_CLK_ENABLE __BITS(17, 16)
+#define CCM_CCGR2_IOMUX_IPT_CLK_IO_CLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR2_IIM_CLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR2_I2C3_SERIAL_CLK_ENABLE __BITS(11, 10)
+#define CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE __BITS(9, 8)
+#define CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE __BITS(7, 6)
+#define CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE __BITS(1, 0)
+#define CCM_CCGR3 0x00000074
+#define CCM_CCGR3_OPENVGAXICLK_CLK_ROOT_ENABLE __BITS(31, 30)
+#define CCM_CCGR3_OCRAM_CLK_ENABLE __BITS(29, 28)
+#define CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_ENABLE __BITS(25, 24)
+#define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_ENABLE __BITS(23, 22)
+#define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE __BITS(21, 20)
+#define CCM_CCGR3_MLB_CLK_ENABLE __BITS(19, 18)
+#define CCM_CCGR3_MIPI_CORE_CFG_CLK_ENABLE __BITS(17, 16)
+#define CCM_CCGR3_LDB_DI1_CLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR3_LDB_DI0_CLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR3_IPU2_IPU_DI1_CLK_ENABLE __BITS(11, 10)
+#define CCM_CCGR3_IPU2_IPU_DI0_CLK_ENABLE __BITS(9, 8)
+#define CCM_CCGR3_IPU2_IPU_CLK_ENABLE __BITS(7, 6)
+#define CCM_CCGR3_IPU1_IPU_DI1_CLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR3_IPU1_IPU_DI0_CLK_ENABLE __BITS(3, 2)
+#define CCM_CCGR3_IPU1_IPU_CLK_ENABLE __BITS(1, 0)
+#define CCM_CCGR4 0x00000078
+#define CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE __BITS(31, 30)
+#define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE __BITS(29, 28)
+#define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE __BITS(27, 26)
+#define CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE __BITS(25, 24)
+#define CCM_CCGR4_PWM4_CLK_ENABLE __BITS(23, 22)
+#define CCM_CCGR4_PWM3_CLK_ENABLE __BITS(21, 20)
+#define CCM_CCGR4_PWM2_CLK_ENABLE __BITS(19, 18)
+#define CCM_CCGR4_PWM1_CLK_ENABLE __BITS(17, 16)
+#define CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE __BITS(9, 8)
+#define CCM_CCGR4_PCIE_ROOT_ENABLE __BITS(1, 0)
#define CCM_CCGR5 0x0000007c
-#define CCM_CCGR5_UART_SERIAL_CLK_ENABLE(n) __SHIFTIN(n, __BITS(27, 26))
-#define CCM_CCGR5_UART_CLK_ENABLE(n) __SHIFTIN(n, __BITS(25, 24))
-#define CCM_CCGR5_SSI3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(23, 22))
-#define CCM_CCGR5_SSI2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(21, 20))
-#define CCM_CCGR5_SSI1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(19, 18))
-#define CCM_CCGR5_SPDIF_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
-#define CCM_CCGR5_SPBA_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
-#define CCM_CCGR5_SDMA_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
-#define CCM_CCGR5_100M_CLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
-#define CCM_CCGR5_ROM_CLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
+#define CCM_CCGR5_UART_SERIAL_CLK_ENABLE __BITS(27, 26)
+#define CCM_CCGR5_UART_CLK_ENABLE __BITS(25, 24)
+#define CCM_CCGR5_SSI3_CLK_ENABLE __BITS(23, 22)
+#define CCM_CCGR5_SSI2_CLK_ENABLE __BITS(21, 20)
+#define CCM_CCGR5_SSI1_CLK_ENABLE __BITS(19, 18)
+#define CCM_CCGR5_SPDIF_CLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR5_SPBA_CLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR5_SDMA_CLK_ENABLE __BITS(7, 6)
+#define CCM_CCGR5_SATA_CLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR5_ROM_CLK_ENABLE __BITS(1, 0)
#define CCM_CCGR6 0x00000080
-#define CCM_CCGR6_VPU_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
-#define CCM_CCGR6_VDOAXICLK_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
-#define CCM_CCGR6_EIM_SLOW_CLK_ENABLE(n) __SHIFTIN(n, __BITS(11, 10))
-#define CCM_CCGR6_USDHC4_CLK_ENABLE(n) __SHIFTIN(n, __BITS(9, 8))
-#define CCM_CCGR6_USDHC3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
-#define CCM_CCGR6_USDHC2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
-#define CCM_CCGR6_USDHC1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(3, 2))
-#define CCM_CCGR6_USBOH3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
+#define CCM_CCGR6_VPU_CLK_ENABLE __BITS(15, 14)
+#define CCM_CCGR6_VDOAXICLK_CLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR6_EIM_SLOW_CLK_ENABLE __BITS(11, 10)
+#define CCM_CCGR6_USDHC4_CLK_ENABLE __BITS(9, 8)
+#define CCM_CCGR6_USDHC3_CLK_ENABLE __BITS(7, 6)
+#define CCM_CCGR6_USDHC2_CLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR6_USDHC1_CLK_ENABLE __BITS(3, 2)
+#define CCM_CCGR6_USBOH3_CLK_ENABLE __BITS(1, 0)
#define CCM_ANALOG_PLL_ARM 0x00000000 /* = 020c8000 */
#define CCM_ANALOG_PLL_ARM_LOCK __BIT(31)
@@ -301,6 +343,7 @@
#define CCM_ANALOG_PLL_SYS_SET 0x00000034
#define CCM_ANALOG_PLL_SYS_CLR 0x00000038
#define CCM_ANALOG_PLL_SYS_TOG 0x0000003c
+#define CCM_ANALOG_PLL_SYS_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC __BITS(15, 14)
#define CCM_ANALOG_PLL_SYS_ENABLE __BIT(13)
#define CCM_ANALOG_PLL_SYS_DIV_SELECT __BIT(0)
@@ -312,6 +355,7 @@
#define CCM_ANALOG_PLL_AUDIO_CLR 0x00000078
#define CCM_ANALOG_PLL_AUDIO_TOG 0x0000007c
#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT __BITS(20, 19)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC __BITS(15, 14)
#define CCM_ANALOG_PLL_AUDIO_ENABLE __BIT(13)
#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT __BITS(6, 0)
@@ -319,6 +363,7 @@
#define CCM_ANALOG_PLL_AUDIO_DENOM 0x00000090
#define CCM_ANALOG_PLL_VIDEO 0x000000a0
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT __BITS(20, 19)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC __BITS(15, 14)
#define CCM_ANALOG_PLL_VIDEO_ENABLE __BIT(13)
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT __BITS(6, 0)
@@ -346,10 +391,7 @@
#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN __BIT(13) /* iMX6UL */
#define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */
#define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12)
-#define CCM_ANALOG_PLL_ENET1_DIV_SELECT(d) __SHIFTIN(d, __BITS(2, 1))
-#define CCM_ANALOG_PLL_ENET1_DIV_SELECT_MASK __BITS(3, 2)
-#define CCM_ANALOG_PLL_ENET_DIV_SELECT(d) __SHIFTIN(d, __BITS(1, 0))
-#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK __BITS(1, 0)
+#define CCM_ANALOG_PLL_ENET_DIV_SELECT __BITS(1, 0)
#define CCM_ANALOG_PFD_480 0x000000f0
#define CCM_ANALOG_PFD_480_SET 0x000000f4
#define CCM_ANALOG_PFD_480_CLR 0x000000f8
@@ -398,7 +440,23 @@
#define CCM_ANALOG_MISC2_SET 0x00000174
#define CCM_ANALOG_MISC2_CLR 0x00000178
#define CCM_ANALOG_MISC2_TOG 0x0000017C
-
+#define CCM_ANALOG_MISC2_VIDEO_DIV __BITS(31, 30)
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME __BITS(29, 28)
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME __BITS(27, 26)
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME __BITS(25, 24)
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB __BIT(23)
+#define CCM_ANALOG_MISC2_REG2_OK __BIT(22)
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO __BIT(21)
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS __BIT(19)
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET __BITS(18, 16)
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB __BIT(15)
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO __BIT(13)
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS __BIT(11)
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET __BITS(10, 8)
+#define CCM_ANALOG_MISC2_PLL3_DISABLE __BIT(7)
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO __BIT(5)
+#define CCM_ANALOG_MISC2_REG0_BO_STATUS __BIT(3)
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET __BITS(2, 0)
#define CCM_TEMPMON_TEMPSENSE0 0x00000180
#define CCM_TEMPMON_TEMPSENSE0_ALARM_VALUE __BIT(31, 30)
@@ -409,7 +467,6 @@
#define CCM_TEMPMON_TEMPSENSE1 0x00000180
#define CCM_TEMPMON_TEMPSENSE1_MEASURE_FREQ __BITS(15, 0)
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