[src/trunk]: src/sys/arch/x86/include Add Intel Deterministic Address Transla...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5fb46db9f16c
branches:  trunk
changeset: 320929:5fb46db9f16c
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Mar 05 05:44:07 2018 +0000

description:
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

diffstat:

 sys/arch/x86/include/cacheinfo.h  |   3 ++-
 sys/arch/x86/include/specialreg.h |  32 +++++++++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 2 deletions(-)

diffs (63 lines):

diff -r 21a530346860 -r 5fb46db9f16c sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Mon Mar 05 04:59:54 2018 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Mon Mar 05 05:44:07 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.22 2016/04/27 08:47:03 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.23 2018/03/05 05:44:07 msaitoh Exp $   */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -333,6 +333,7 @@
 __CI_TBL(CAI_L3CACHE,  0xec,   24,24 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_PREFETCH, 0xf0,    0,               0, 64, NULL), \
 __CI_TBL(CAI_PREFETCH, 0xf1,    0,               0,128, NULL), \
+/* 0xfe means no TLB information in CPUID leaf 2 (and use leaf 0x18) */ \
 /* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
 __CI_TBL(0,               0,    0,               0,  0, NULL)  \
 }
diff -r 21a530346860 -r 5fb46db9f16c sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Mon Mar 05 04:59:54 2018 +0000
+++ b/sys/arch/x86/include/specialreg.h Mon Mar 05 05:44:07 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.111 2018/01/15 08:17:20 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.112 2018/03/05 05:44:07 msaitoh Exp $ */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -456,6 +456,36 @@
                        "\06" "LZCNT"                           \
        "\11" "PREFETCHW"
 
+
+/*
+ * Intel Deterministic Address Translation Parameter Leaf
+ * Fn0000_0018
+ */
+
+/* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */
+
+/* %ebx */
+#define CPUID_DATP_PGSIZE      __BITS(3, 0)    /* page size */
+#define CPUID_DATP_PGSIZE_4KB  __BIT(0)        /* 4KB page support */
+#define CPUID_DATP_PGSIZE_2MB  __BIT(1)        /* 2MB page support */
+#define CPUID_DATP_PGSIZE_4MB  __BIT(2)        /* 4MB page support */
+#define CPUID_DATP_PGSIZE_1GB  __BIT(3)        /* 1GB page support */
+#define CPUID_DATP_PARTITIONING        __BITS(10, 8)   /* Partitioning */
+#define CPUID_DATP_WAYS                __BITS(31, 16)  /* Ways of associativity */
+
+/* Number of sets: %ecx */
+
+/* %edx */
+#define CPUID_DATP_TCTYPE      __BITS(4, 0)    /* Translation Cache type */
+#define CPUID_DATP_TCTYPE_N    0               /*   NULL (not valid) */
+#define CPUID_DATP_TCTYPE_D    1               /*   Data TLB */
+#define CPUID_DATP_TCTYPE_I    2               /*   Instruction TLB */
+#define CPUID_DATP_TCTYPE_U    3               /*   Unified TLB */
+#define CPUID_DATP_TCLEVEL     __BITS(7, 5)    /* TLB level (start at 1) */
+#define CPUID_DATP_FULLASSOC   __BIT(8)        /* Full associative */
+#define CPUID_DATP_SHAREING    __BITS(25, 14)  /* shareing */
+
+
 /* AMD/VIA Fn80000001 extended features - %edx */
 /*     CPUID_SYSCALL                      SYSCALL/SYSRET */
 #define CPUID_MPC      0x00080000      /* Multiprocessing Capable */