[src/trunk]: src/sys/dev/fdt fdtbus_clock_assign: simplify

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1f640a78d306
branches:  trunk
changeset: 319931:1f640a78d306
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Jun 16 00:12:35 2018 +0000

description:
fdtbus_clock_assign: simplify

diffstat:

 sys/dev/fdt/fdt_clock.c |  27 ++++++++++++++++-----------
 1 files changed, 16 insertions(+), 11 deletions(-)

diffs (64 lines):

diff -r 71faa305cb76 -r 1f640a78d306 sys/dev/fdt/fdt_clock.c
--- a/sys/dev/fdt/fdt_clock.c   Fri Jun 15 23:57:55 2018 +0000
+++ b/sys/dev/fdt/fdt_clock.c   Sat Jun 16 00:12:35 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fdt_clock.c,v 1.3 2018/06/12 10:28:55 jmcneill Exp $ */
+/* $NetBSD: fdt_clock.c,v 1.4 2018/06/16 00:12:35 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fdt_clock.c,v 1.3 2018/06/12 10:28:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fdt_clock.c,v 1.4 2018/06/16 00:12:35 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -224,6 +224,8 @@
                rates_len = 0;
 
        const u_int nclocks = fdtbus_clock_count_prop(phandle, "assigned-clocks");
+       const u_int nparents = fdtbus_clock_count_prop(phandle, "assigned-clock-parents");
+       const u_int nrates = rates_len / sizeof(*rates);
 
        for (index = 0; index < nclocks; index++) {
                clk = fdtbus_clock_get_index_prop(phandle, index, "assigned-clocks");
@@ -232,24 +234,27 @@
                        continue;
                }
 
-               clk_parent = fdtbus_clock_get_index_prop(phandle, index, "assigned-clock-parents");
-               if (clk_parent != NULL) {
-                       error = clk_set_parent(clk, clk_parent);
-                       if (error != 0) {
-                               aprint_error("clk: failed to set %s parent to %s, error %d\n",
-                                   clk->name, clk_parent->name, error);
+               if (index < nparents) {
+                       clk_parent = fdtbus_clock_get_index_prop(phandle, index, "assigned-clock-parents");
+                       if (clk_parent != NULL) {
+                               error = clk_set_parent(clk, clk_parent);
+                               if (error != 0) {
+                                       aprint_error("clk: failed to set %s parent to %s, error %d\n",
+                                           clk->name, clk_parent->name, error);
+                               }
+                       } else {
+                               aprint_debug("clk: failed to set %s parent (not found)\n", clk->name);
                        }
                }
 
-               if (rates_len >= sizeof(*rates)) {
-                       const u_int rate = be32dec(rates);
+               if (index < nrates) {
+                       const u_int rate = be32toh(rates[index]);
                        if (rate != 0) {
                                error = clk_set_rate(clk, rate);
                                if (error != 0)
                                        aprint_error("clk: failed to set %s rate to %u Hz, error %d\n",
                                            clk->name, rate, error);
                        }
-                       rates_len -= sizeof(*rates);
                }
        }
 }