[src/trunk]: src/sys/dev/pci s/regisrer/register/. No functional change.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bcff363f7ba5
branches:  trunk
changeset: 319852:bcff363f7ba5
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Thu Jun 14 07:19:47 2018 +0000

description:
s/regisrer/register/. No functional change.

diffstat:

 sys/dev/pci/if_skreg.h |  10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (45 lines):

diff -r 1e133cfb3dab -r bcff363f7ba5 sys/dev/pci/if_skreg.h
--- a/sys/dev/pci/if_skreg.h    Thu Jun 14 06:58:15 2018 +0000
+++ b/sys/dev/pci/if_skreg.h    Thu Jun 14 07:19:47 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_skreg.h,v 1.20 2018/06/14 06:58:15 msaitoh Exp $ */
+/* $NetBSD: if_skreg.h,v 1.21 2018/06/14 07:19:47 msaitoh Exp $ */
 
 /*-
  * Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -1079,7 +1079,7 @@
 #define SK_RBCTL_STORENFWD_OFF 0x10
 #define SK_RBCTL_STORENFWD_ON  0x20
 
-/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
+/* Block 24 -- RX MAC FIFO 1 registers and LINK_SYNC counter */
 #define SK_RXF1_END            0x0C00
 #define SK_RXF1_WPTR           0x0C04
 #define SK_RXF1_RPTR           0x0C0C
@@ -1128,7 +1128,7 @@
 
 #define SK_RFCTL_FIFO_THRESHOLD 0x0a    /* flush threshold (default) */
 
-/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
+/* Block 25 -- RX MAC FIFO 2 registers and LINK_SYNC counter */
 #define SK_RXF2_END            0x0C80
 #define SK_RXF2_WPTR           0x0C84
 #define SK_RXF2_RPTR           0x0C8C
@@ -1174,7 +1174,7 @@
 #define SK_LINKLED_BLINK_OFF           0x0010
 #define SK_LINKLED_BLINK_ON            0x0020
 
-/* Block 26 -- TX MAC FIFO 1 regisrers  */
+/* Block 26 -- TX MAC FIFO 1 registers  */
 #define SK_TXF1_END            0x0D00
 #define SK_TXF1_WPTR           0x0D04
 #define SK_TXF1_RPTR           0x0D0C
@@ -1213,7 +1213,7 @@
 #define SK_TFCTL_RESET_CLEAR   0x00000002      /* MAC FIFO Reset Clear */
 #define SK_TFCTL_RESET_SET     0x00000001      /* MAC FIFO Reset Set */
 
-/* Block 27 -- TX MAC FIFO 2 regisrers  */
+/* Block 27 -- TX MAC FIFO 2 registers  */
 #define SK_TXF2_END            0x0D80
 #define SK_TXF2_WPTR           0x0D84
 #define SK_TXF2_RPTR           0x0D8C