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[src/FREEBSD]: src/sys/external/bsd/ena-com Introduce HAL for Am...



details:   https://anonhg.NetBSD.org/src/rev/eb699a021bed
branches:  FREEBSD
changeset: 319160:eb699a021bed
user:      jdolecek <jdolecek%NetBSD.org@localhost>
date:      Sat May 19 08:56:05 2018 +0000

description:
Introduce HAL for Amazon Elastic Network Adapter (ENA)

This commit adds HAL (Hardware Abstraction Layer) code
for Amazon Elastic Network Adapter (ENA).

Version: 1.1.4.3

Obtained from: Amazon.com, Inc. via FreeBSD

diffstat:

 sys/external/bsd/ena-com/ena_admin_defs.h           |  1412 +++++++++
 sys/external/bsd/ena-com/ena_com.c                  |  2980 +++++++++++++++++++
 sys/external/bsd/ena-com/ena_com.h                  |  1120 +++++++
 sys/external/bsd/ena-com/ena_common_defs.h          |    50 +
 sys/external/bsd/ena-com/ena_defs/ena_admin_defs.h  |  1484 +++++++++
 sys/external/bsd/ena-com/ena_defs/ena_common_defs.h |    49 +
 sys/external/bsd/ena-com/ena_defs/ena_eth_io_defs.h |   959 ++++++
 sys/external/bsd/ena-com/ena_defs/ena_gen_info.h    |    34 +
 sys/external/bsd/ena-com/ena_defs/ena_includes.h    |     4 +
 sys/external/bsd/ena-com/ena_defs/ena_regs_defs.h   |   168 +
 sys/external/bsd/ena-com/ena_eth_com.c              |   624 +++
 sys/external/bsd/ena-com/ena_eth_com.h              |   186 +
 sys/external/bsd/ena-com/ena_eth_io_defs.h          |   960 ++++++
 sys/external/bsd/ena-com/ena_plat.h                 |   377 ++
 sys/external/bsd/ena-com/ena_regs_defs.h            |   137 +
 15 files changed, 10544 insertions(+), 0 deletions(-)

diffs (truncated from 10604 to 300 lines):

diff -r 8748e68a240f -r eb699a021bed sys/external/bsd/ena-com/ena_admin_defs.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/external/bsd/ena-com/ena_admin_defs.h Sat May 19 08:56:05 2018 +0000
@@ -0,0 +1,1412 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ENA_ADMIN_H_
+#define _ENA_ADMIN_H_
+
+enum ena_admin_aq_opcode {
+       ENA_ADMIN_CREATE_SQ     = 1,
+
+       ENA_ADMIN_DESTROY_SQ    = 2,
+
+       ENA_ADMIN_CREATE_CQ     = 3,
+
+       ENA_ADMIN_DESTROY_CQ    = 4,
+
+       ENA_ADMIN_GET_FEATURE   = 8,
+
+       ENA_ADMIN_SET_FEATURE   = 9,
+
+       ENA_ADMIN_GET_STATS     = 11,
+};
+
+enum ena_admin_aq_completion_status {
+       ENA_ADMIN_SUCCESS                       = 0,
+
+       ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE   = 1,
+
+       ENA_ADMIN_BAD_OPCODE                    = 2,
+
+       ENA_ADMIN_UNSUPPORTED_OPCODE            = 3,
+
+       ENA_ADMIN_MALFORMED_REQUEST             = 4,
+
+       /* Additional status is provided in ACQ entry extended_status */
+       ENA_ADMIN_ILLEGAL_PARAMETER             = 5,
+
+       ENA_ADMIN_UNKNOWN_ERROR                 = 6,
+};
+
+enum ena_admin_aq_feature_id {
+       ENA_ADMIN_DEVICE_ATTRIBUTES             = 1,
+
+       ENA_ADMIN_MAX_QUEUES_NUM                = 2,
+
+       ENA_ADMIN_HW_HINTS                      = 3,
+
+       ENA_ADMIN_RSS_HASH_FUNCTION             = 10,
+
+       ENA_ADMIN_STATELESS_OFFLOAD_CONFIG      = 11,
+
+       ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG  = 12,
+
+       ENA_ADMIN_MTU                           = 14,
+
+       ENA_ADMIN_RSS_HASH_INPUT                = 18,
+
+       ENA_ADMIN_INTERRUPT_MODERATION          = 20,
+
+       ENA_ADMIN_AENQ_CONFIG                   = 26,
+
+       ENA_ADMIN_LINK_CONFIG                   = 27,
+
+       ENA_ADMIN_HOST_ATTR_CONFIG              = 28,
+
+       ENA_ADMIN_FEATURES_OPCODE_NUM           = 32,
+};
+
+enum ena_admin_placement_policy_type {
+       /* descriptors and headers are in host memory */
+       ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
+
+       /* descriptors and headers are in device memory (a.k.a Low Latency
+        * Queue)
+        */
+       ENA_ADMIN_PLACEMENT_POLICY_DEV  = 3,
+};
+
+enum ena_admin_link_types {
+       ENA_ADMIN_LINK_SPEED_1G         = 0x1,
+
+       ENA_ADMIN_LINK_SPEED_2_HALF_G   = 0x2,
+
+       ENA_ADMIN_LINK_SPEED_5G         = 0x4,
+
+       ENA_ADMIN_LINK_SPEED_10G        = 0x8,
+
+       ENA_ADMIN_LINK_SPEED_25G        = 0x10,
+
+       ENA_ADMIN_LINK_SPEED_40G        = 0x20,
+
+       ENA_ADMIN_LINK_SPEED_50G        = 0x40,
+
+       ENA_ADMIN_LINK_SPEED_100G       = 0x80,
+
+       ENA_ADMIN_LINK_SPEED_200G       = 0x100,
+
+       ENA_ADMIN_LINK_SPEED_400G       = 0x200,
+};
+
+enum ena_admin_completion_policy_type {
+       /* completion queue entry for each sq descriptor */
+       ENA_ADMIN_COMPLETION_POLICY_DESC                = 0,
+
+       /* completion queue entry upon request in sq descriptor */
+       ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND      = 1,
+
+       /* current queue head pointer is updated in OS memory upon sq
+        * descriptor request
+        */
+       ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND      = 2,
+
+       /* current queue head pointer is updated in OS memory for each sq
+        * descriptor
+        */
+       ENA_ADMIN_COMPLETION_POLICY_HEAD                = 3,
+};
+
+/* basic stats return ena_admin_basic_stats while extanded stats return a
+ * buffer (string format) with additional statistics per queue and per
+ * device id
+ */
+enum ena_admin_get_stats_type {
+       ENA_ADMIN_GET_STATS_TYPE_BASIC          = 0,
+
+       ENA_ADMIN_GET_STATS_TYPE_EXTENDED       = 1,
+};
+
+enum ena_admin_get_stats_scope {
+       ENA_ADMIN_SPECIFIC_QUEUE        = 0,
+
+       ENA_ADMIN_ETH_TRAFFIC           = 1,
+};
+
+struct ena_admin_aq_common_desc {
+       /* 11:0 : command_id
+        * 15:12 : reserved12
+        */
+       uint16_t command_id;
+
+       /* as appears in ena_admin_aq_opcode */
+       uint8_t opcode;
+
+       /* 0 : phase
+        * 1 : ctrl_data - control buffer address valid
+        * 2 : ctrl_data_indirect - control buffer address
+        *    points to list of pages with addresses of control
+        *    buffers
+        * 7:3 : reserved3
+        */
+       uint8_t flags;
+};
+
+/* used in ena_admin_aq_entry. Can point directly to control data, or to a
+ * page list chunk. Used also at the end of indirect mode page list chunks,
+ * for chaining.
+ */
+struct ena_admin_ctrl_buff_info {
+       uint32_t length;
+
+       struct ena_common_mem_addr address;
+};
+
+struct ena_admin_sq {
+       uint16_t sq_idx;
+
+       /* 4:0 : reserved
+        * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
+        */
+       uint8_t sq_identity;
+
+       uint8_t reserved1;
+};
+
+struct ena_admin_aq_entry {
+       struct ena_admin_aq_common_desc aq_common_descriptor;
+
+       union {
+               uint32_t inline_data_w1[3];
+
+               struct ena_admin_ctrl_buff_info control_buffer;
+       } u;
+
+       uint32_t inline_data_w4[12];
+};
+
+struct ena_admin_acq_common_desc {
+       /* command identifier to associate it with the aq descriptor
+        * 11:0 : command_id
+        * 15:12 : reserved12
+        */
+       uint16_t command;
+
+       uint8_t status;
+
+       /* 0 : phase
+        * 7:1 : reserved1
+        */
+       uint8_t flags;
+
+       uint16_t extended_status;
+
+       /* serves as a hint what AQ entries can be revoked */
+       uint16_t sq_head_indx;
+};
+
+struct ena_admin_acq_entry {
+       struct ena_admin_acq_common_desc acq_common_descriptor;
+
+       uint32_t response_specific_data[14];
+};
+
+struct ena_admin_aq_create_sq_cmd {
+       struct ena_admin_aq_common_desc aq_common_descriptor;
+
+       /* 4:0 : reserved0_w1
+        * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
+        */
+       uint8_t sq_identity;
+
+       uint8_t reserved8_w1;
+
+       /* 3:0 : placement_policy - Describing where the SQ
+        *    descriptor ring and the SQ packet headers reside:
+        *    0x1 - descriptors and headers are in OS memory,
+        *    0x3 - descriptors and headers in device memory
+        *    (a.k.a Low Latency Queue)
+        * 6:4 : completion_policy - Describing what policy
+        *    to use for generation completion entry (cqe) in
+        *    the CQ associated with this SQ: 0x0 - cqe for each
+        *    sq descriptor, 0x1 - cqe upon request in sq
+        *    descriptor, 0x2 - current queue head pointer is
+        *    updated in OS memory upon sq descriptor request
+        *    0x3 - current queue head pointer is updated in OS
+        *    memory for each sq descriptor
+        * 7 : reserved15_w1
+        */
+       uint8_t sq_caps_2;
+
+       /* 0 : is_physically_contiguous - Described if the
+        *    queue ring memory is allocated in physical
+        *    contiguous pages or split.
+        * 7:1 : reserved17_w1
+        */
+       uint8_t sq_caps_3;
+
+       /* associated completion queue id. This CQ must be created prior to
+        *    SQ creation
+        */
+       uint16_t cq_idx;
+
+       /* submission queue depth in entries */
+       uint16_t sq_depth;
+
+       /* SQ physical base address in OS memory. This field should not be
+        * used for Low Latency queues. Has to be page aligned.
+        */
+       struct ena_common_mem_addr sq_ba;
+
+       /* specifies queue head writeback location in OS memory. Valid if
+        * completion_policy is set to completion_policy_head_on_demand or
+        * completion_policy_head. Has to be cache aligned
+        */
+       struct ena_common_mem_addr sq_head_writeback;
+
+       uint32_t reserved0_w7;
+



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