[src/trunk]: src/sys/arch/aarch64/aarch64 allow to execute cache...

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7dbf8b0b5976
branches:  trunk
changeset: 319108:7dbf8b0b5976
user:      ryo <ryo%NetBSD.org@localhost>
date:      Thu May 17 08:24:28 2018 +0000

description:
allow to execute cache operation (DC CVAU,DC CIVAC, DC CVAC, IC IVAU) from userland.

diffstat:

 sys/arch/aarch64/aarch64/locore.S |  6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diffs (34 lines):

diff -r e131ac8a3bc9 -r 7dbf8b0b5976 sys/arch/aarch64/aarch64/locore.S
--- a/sys/arch/aarch64/aarch64/locore.S Thu May 17 07:30:13 2018 +0000
+++ b/sys/arch/aarch64/aarch64/locore.S Thu May 17 08:24:28 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.5 2018/04/01 04:35:03 ryo Exp $   */
+/*     $NetBSD: locore.S,v 1.6 2018/05/17 08:24:28 ryo Exp $   */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -36,7 +36,7 @@
 #include <aarch64/pte.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.5 2018/04/01 04:35:03 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.6 2018/05/17 08:24:28 ryo Exp $")
 
 /* #define DEBUG_LOCORE */
 /* #define DEBUG_MMU */
@@ -692,6 +692,7 @@
        .quad ( \
            SCTLR_LSMAOE |  /* Load/Store Multiple Atomicity and Ordering */ \
            SCTLR_nTLSMD |  /* no Trap Load/Store Multiple to Device */ \
+           SCTLR_UCI |     /* Enables EL0 DC {CVAU,CIVAC,CVAC}, IC IVAU */ \
            SCTLR_SPAN |    /* This field resets to 1 */ \
            SCTLR_UCT |     /* Enables EL0 access to the CTR_EL0 */ \
            SCTLR_DZE |     /* Enables access to the DC ZVA instruction */ \
@@ -705,7 +706,6 @@
            0)
 sctlr_clear:
        .quad ( \
-           SCTLR_UCI |     /* Enable EL0  DC {CVAU,CIVAC,CVAC}, IC IVAU */ \
            SCTLR_IESB |    /* Enable Implicit ErrorSynchronizationBarrier */ \
            SCTLR_WXN |     /* Write permission implies Execute Never (W^X) */ \
            SCTLR_nTWE |    /* EL0 WFE non-trapping */ \