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[src/trunk]: src/sys/arch/macppc/macppc deal with IPIs on U3/HT ...
details: https://anonhg.NetBSD.org/src/rev/f258110b15ca
branches: trunk
changeset: 318989:f258110b15ca
user: macallan <macallan%NetBSD.org@localhost>
date: Fri May 11 22:48:38 2018 +0000
description:
deal with IPIs on U3/HT machines, only install OpenPIC IPI goop on actual
OpenPIC hardware
diffstat:
sys/arch/macppc/macppc/cpu.c | 21 +++++---
sys/arch/macppc/macppc/interrupts.c | 16 +++--
sys/arch/macppc/macppc/pic_u3_ht.c | 89 ++++++++++++++++++++++++++++++++++++-
3 files changed, 109 insertions(+), 17 deletions(-)
diffs (279 lines):
diff -r b1394597b8a0 -r f258110b15ca sys/arch/macppc/macppc/cpu.c
--- a/sys/arch/macppc/macppc/cpu.c Fri May 11 22:39:59 2018 +0000
+++ b/sys/arch/macppc/macppc/cpu.c Fri May 11 22:48:38 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.63 2018/03/29 16:19:46 macallan Exp $ */
+/* $NetBSD: cpu.c,v 1.64 2018/05/11 22:48:38 macallan Exp $ */
/*-
* Copyright (c) 2001 Tsubai Masanari.
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.63 2018/03/29 16:19:46 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.64 2018/05/11 22:48:38 macallan Exp $");
#include "opt_ppcparam.h"
#include "opt_multiprocessor.h"
@@ -204,11 +204,14 @@
#ifdef MULTIPROCESSOR
+extern int have_u3_ht(void);
+extern void __u3_ht_set_priority(int, int);
+
int
md_setup_trampoline(volatile struct cpu_hatch_data *h, struct cpu_info *ci)
{
#ifdef OPENPIC
- if (openpic_base) {
+ if ((openpic_base != NULL) || have_u3_ht()) {
uint32_t kl_base = (uint32_t)oea_mapiodev(0x80000000, 0x1000);
uint32_t gpio = kl_base + 0x5c; /* XXX */
u_int node, off;
@@ -253,7 +256,7 @@
md_presync_timebase(volatile struct cpu_hatch_data *h)
{
#ifdef OPENPIC
- if (openpic_base) {
+ if ((openpic_base != NULL) || have_u3_ht()) {
uint64_t tb;
/* Sync timebase. */
@@ -283,7 +286,7 @@
{
int i;
#ifdef OPENPIC
- if (!openpic_base) {
+ if (!((openpic_base != NULL) || have_u3_ht())) {
#endif
/*
* wait for secondary spin up (1.5ms @ 604/200MHz)
@@ -306,7 +309,7 @@
md_sync_timebase(volatile struct cpu_hatch_data *h)
{
#ifdef OPENPIC
- if (openpic_base) {
+ if ((openpic_base != NULL) || have_u3_ht()) {
/* Sync timebase. */
u_int tbu = h->hatch_tbu;
u_int tbl = h->hatch_tbl;
@@ -324,9 +327,11 @@
md_setup_interrupts(void)
{
#ifdef OPENPIC
- if (openpic_base)
+ if (openpic_base) {
openpic_set_priority(cpu_number(), 0);
- else
+ } else if (have_u3_ht()) {
+ __u3_ht_set_priority(cpu_number(), 0);
+ } else
#endif /* OPENPIC */
out32(HH_INTR_SECONDARY, ~0); /* Reset interrupt. */
}
diff -r b1394597b8a0 -r f258110b15ca sys/arch/macppc/macppc/interrupts.c
--- a/sys/arch/macppc/macppc/interrupts.c Fri May 11 22:39:59 2018 +0000
+++ b/sys/arch/macppc/macppc/interrupts.c Fri May 11 22:48:38 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupts.c,v 1.6 2018/03/22 21:28:58 macallan Exp $ */
+/* $NetBSD: interrupts.c,v 1.7 2018/05/11 22:48:38 macallan Exp $ */
/*-
* Copyright (c) 2007 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupts.c,v 1.6 2018/03/22 21:28:58 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupts.c,v 1.7 2018/05/11 22:48:38 macallan Exp $");
#include "opt_multiprocessor.h"
@@ -126,19 +126,21 @@
goto done;
#endif
#if NPIC_OPENPIC > 0
- if (init_openpic(0))
+ if (init_openpic(0)) {
+#ifdef MULTIPROCESSOR
+ setup_openpic_ipi();
+#endif
goto done;
+ }
#endif
panic("%s: no supported interrupt controller found", __func__);
done:
oea_install_extint(pic_ext_intr);
#ifdef MULTIPROCESSOR
-#if NPIC_OPENPIC > 0
- setup_openpic_ipi();
-#else /*NPIC_OPENPIC*/
+#if (NPIC_OHARE + NPIC_HEATHROW) > 0
if (OF_finddevice("/hammerhead") != -1)
setup_hammerhead_ipi();
-#endif /*NPIC_OPENPIC*/
+#endif
#endif /*MULTIPROCESSOR*/
}
diff -r b1394597b8a0 -r f258110b15ca sys/arch/macppc/macppc/pic_u3_ht.c
--- a/sys/arch/macppc/macppc/pic_u3_ht.c Fri May 11 22:39:59 2018 +0000
+++ b/sys/arch/macppc/macppc/pic_u3_ht.c Fri May 11 22:48:38 2018 +0000
@@ -32,6 +32,8 @@
#include <sys/param.h>
#include <sys/kmem.h>
#include <sys/kernel.h>
+#include <sys/atomic.h>
+#include <sys/cpu.h>
#include <machine/pio.h>
#include <powerpc/openpic.h>
@@ -92,6 +94,7 @@
static void u3_ht_ack_ht_irq(struct u3_ht_ops *, int);
static void u3_ht_set_priority(struct u3_ht_ops *, int, int);
+void __u3_ht_set_priority(int, int);
static int u3_ht_read_irq(struct u3_ht_ops *, int);
static void u3_ht_eoi(struct u3_ht_ops *, int);
@@ -112,6 +115,17 @@
NULL
};
+static struct u3_ht_ops *u3ht0 = NULL;
+int have_u3_ht(void);
+
+#ifdef MULTIPROCESSOR
+
+extern struct ipi_ops ipiops;
+static void u3_ht_send_ipi(cpuid_t, uint32_t);
+static void u3_ht_establish_ipi(int, int, void *);
+
+#endif
+
int init_u3_ht(void)
{
int u4, pic;
@@ -170,7 +184,7 @@
struct u3_ht_ops *u3_ht;
struct pic_ops *pic;
int irq;
- u_int x;
+ uint32_t x;
u3_ht = kmem_alloc(sizeof(struct u3_ht_ops), KM_SLEEP);
bzero(u3_ht, sizeof(struct u3_ht_ops));
@@ -203,7 +217,8 @@
"Supports %d CPUs and %d interrupt sources.\n",
x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
- pic->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1;
+ /* up to 128 interrupt sources, plus IPI */
+ pic->pic_numintrs = 129;
pic->pic_cookie = (void *) addr;
pic->pic_enable_irq = u3_ht_enable_irq;
pic->pic_reenable_irq = u3_ht_enable_irq;
@@ -247,6 +262,18 @@
u3_ht_eoi(u3_ht, 0);
}
+#ifdef MULTIPROCESSOR
+ ipiops.ppc_send_ipi = u3_ht_send_ipi;
+ ipiops.ppc_establish_ipi = u3_ht_establish_ipi;
+ ipiops.ppc_ipi_vector = IPI_VECTOR;
+
+ x = u3_ht_read(u3_ht, OPENPIC_IPI_VECTOR(1));
+ x &= ~(OPENPIC_IMASK | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK);
+ x |= (15 << OPENPIC_PRIORITY_SHIFT) | ipiops.ppc_ipi_vector;
+ u3_ht_write(u3_ht, OPENPIC_IPI_VECTOR(1), x);
+ u3ht0 = u3_ht;
+#endif /* MULTIPROCESSOR */
+
return u3_ht;
}
@@ -338,6 +365,9 @@
struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
u_int x;
+#ifdef MULTIPROCESSOR
+ if (irq == IPI_VECTOR) return;
+#endif
x = u3_ht_read(u3_ht, OPENPIC_SRC_VECTOR(irq));
x &= ~OPENPIC_IMASK;
u3_ht_write(u3_ht, OPENPIC_SRC_VECTOR(irq), x);
@@ -352,6 +382,9 @@
struct u3_ht_ops *u3_ht = (struct u3_ht_ops *)pic;
u_int x;
+#ifdef MULTIPROCESSOR
+ if (irq == IPI_VECTOR) return;
+#endif
x = u3_ht_read(u3_ht, OPENPIC_SRC_VECTOR(irq));
x |= OPENPIC_IMASK;
u3_ht_write(u3_ht, OPENPIC_SRC_VECTOR(irq), x);
@@ -511,6 +544,14 @@
u3_ht_write(u3_ht, OPENPIC_CPU_PRIORITY(cpu), x);
}
+void
+__u3_ht_set_priority(int cpu, int pri)
+{
+ if (u3ht0 == NULL) return;
+
+ u3_ht_set_priority(u3ht0, cpu, pri);
+}
+
static int
u3_ht_read_irq(struct u3_ht_ops *u3_ht, int cpu)
{
@@ -555,3 +596,47 @@
out32rb(addr, val);
}
+
+#ifdef MULTIPROCESSOR
+
+static void
+u3_ht_send_ipi(cpuid_t target, uint32_t mesg)
+{
+ struct cpu_info * const ci = curcpu();
+ uint32_t cpumask = 0;
+
+ switch (target) {
+ case IPI_DST_ALL:
+ case IPI_DST_NOTME:
+ for (u_int i = 0; i < ncpu; i++) {
+ struct cpu_info * const dst_ci = cpu_lookup(i);
+ if (target == IPI_DST_ALL || dst_ci != ci) {
+ cpumask |= 1 << cpu_index(dst_ci);
+ atomic_or_32(&dst_ci->ci_pending_ipis,
+ mesg);
+ }
+ }
+ break;
+ default: {
+ struct cpu_info * const dst_ci = cpu_lookup(target);
+ cpumask = 1 << cpu_index(dst_ci);
+ atomic_or_32(&dst_ci->ci_pending_ipis, mesg);
+ break;
+ }
+ }
+ u3_ht_write(u3ht0, OPENPIC_IPI(cpu_index(ci), 1), cpumask);
+}
+
+static void
+u3_ht_establish_ipi(int type, int level, void *ih_args)
+{
+ intr_establish(ipiops.ppc_ipi_vector, type, level, ipi_intr, ih_args);
+}
+
+#endif /*MULTIPROCESSOR*/
+
+int
+have_u3_ht(void)
+{
+ return (u3ht0 != NULL);
+}
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