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src: Regen (ticket #723)
details: https://anonhg.NetBSD.org/src/rev/2fd53ec52743
branches: netbsd-8
changeset: 317992:2fd53ec52743
user: martin <martin%NetBSD.org@localhost>
date: Mon Apr 09 18:20:09 2018 +0000
description:
Regen (ticket #723)
diffstat:
sys/dev/pci/pcidevs.h | 605 +-
sys/dev/pci/pcidevs_data.h | 20937 ++++++++++++++++++++++--------------------
2 files changed, 11567 insertions(+), 9975 deletions(-)
diffs (truncated from 27402 to 300 lines):
diff -r aa01317126b8 -r 2fd53ec52743 sys/dev/pci/pcidevs.h
--- a/sys/dev/pci/pcidevs.h Mon Apr 09 18:18:49 2018 +0000
+++ b/sys/dev/pci/pcidevs.h Mon Apr 09 18:20:09 2018 +0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs.h,v 1.1281.2.3 2018/03/08 14:32:49 martin Exp $ */
+/* $NetBSD: pcidevs.h,v 1.1281.2.4 2018/04/09 18:20:09 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.1289.2.3 2018/03/08 14:31:18 martin Exp
+ * NetBSD: pcidevs,v 1.1289.2.4 2018/04/09 18:18:49 martin Exp
*/
/*
@@ -456,7 +456,7 @@
#define PCI_VENDOR_OMEGA 0x119b /* Omega Micro */
#define PCI_VENDOR_ITI 0x119c /* Information Technology Institute */
#define PCI_VENDOR_BUG 0x119d /* Bug Sapporo */
-#define PCI_VENDOR_FUJITSU3 0x119e /* Fujitsu (3th PCI Vendor ID) */
+#define PCI_VENDOR_FUJITSU3 0x119e /* Fujitsu (3rd PCI Vendor ID) */
#define PCI_VENDOR_BULL 0x119f /* Bull Hn Information Systems */
#define PCI_VENDOR_CONVEX 0x11a0 /* Convex Computer */
#define PCI_VENDOR_HAMAMATSU 0x11a1 /* Hamamatsu Photonics */
@@ -639,6 +639,7 @@
#define PCI_VENDOR_FREESCALE 0x1957 /* Freescale Semiconductor */
#define PCI_VENDOR_ATTANSIC 0x1969 /* Attansic Technologies */
#define PCI_VENDOR_JMICRON 0x197b /* JMicron Technology */
+#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines */
#define PCI_VENDOR_HUAWEI 0x19e5 /* Huaewi Technology */
#define PCI_VENDOR_ASPEED 0x1a03 /* ASPEED Technology */
#define PCI_VENDOR_AWT 0x1a3b /* AWT */
@@ -1121,6 +1122,7 @@
#define PCI_PRODUCT_AMD_HUDSON_XHCI 0x7812 /* Hudson USB xHCI Controller */
#define PCI_PRODUCT_AMD_FCH_SDHC 0x7813 /* FCH SD Flash Controller */
#define PCI_PRODUCT_AMD_FCH_XHCI 0x7814 /* FCH USB xHCI Controller */
+#define PCI_PRODUCT_AMD_KERNCZ_SMB 0x790b /* X370/X399 SMBus Controller */
#define PCI_PRODUCT_AMD_RS780_HB 0x9600 /* RS780 Host Bridge */
#define PCI_PRODUCT_AMD_RS880_HB 0x9601 /* RS785/RS880 Host Bridge */
#define PCI_PRODUCT_AMD_RS780_PPB_GFX 0x9602 /* RS780/RS880 PCI-PCI Bridge (int gfx) */
@@ -1927,6 +1929,7 @@
#define PCI_PRODUCT_CAVIUM_NITROX 0x0001 /* Nitrox XL */
/* Chelsio products */
+#define PCI_PRODUCT_CHELSIO_PE9000 0x0020 /* PE9000 10GbE */
#define PCI_PRODUCT_CHELSIO_T302E 0x0021 /* T302e */
#define PCI_PRODUCT_CHELSIO_T310E 0x0022 /* T310e */
#define PCI_PRODUCT_CHELSIO_T320X 0x0023 /* T320x */
@@ -1936,6 +1939,57 @@
#define PCI_PRODUCT_CHELSIO_T3B10 0x0030 /* T3B10 */
#define PCI_PRODUCT_CHELSIO_T3B20 0x0031 /* T3B20 */
#define PCI_PRODUCT_CHELSIO_T3B02 0x0032 /* T3B02 */
+#define PCI_PRODUCT_CHELSIO_T3B04 0x0033 /* T3B04 */
+#define PCI_PRODUCT_CHELSIO_T3C10 0x0035 /* T3C10 */
+#define PCI_PRODUCT_CHELSIO_S320E_CR 0x0036 /* S320E-CR */
+#define PCI_PRODUCT_CHELSIO_N320E_G2 0x0037 /* N320E-G2 */
+#define PCI_PRODUCT_CHELSIO_T440_DBG 0x4400 /* T440-dbg */
+#define PCI_PRODUCT_CHELSIO_T420_CR 0x4401 /* T420-CR */
+#define PCI_PRODUCT_CHELSIO_T422_CR 0x4402 /* T422-CR */
+#define PCI_PRODUCT_CHELSIO_T440_CR 0x4403 /* T440-CR */
+#define PCI_PRODUCT_CHELSIO_T420_BCH 0x4404 /* T420-BCH */
+#define PCI_PRODUCT_CHELSIO_T440_BCH 0x4405 /* T440-BCH */
+#define PCI_PRODUCT_CHELSIO_T440_CH 0x4406 /* T440-CH */
+#define PCI_PRODUCT_CHELSIO_T420_SO 0x4407 /* T420-SO */
+#define PCI_PRODUCT_CHELSIO_T420_CX 0x4408 /* T420-CX */
+#define PCI_PRODUCT_CHELSIO_T420_BT 0x4409 /* T420-BT */
+#define PCI_PRODUCT_CHELSIO_T404_BT 0x440a /* T404-BT */
+#define PCI_PRODUCT_CHELSIO_T440_LP_CR 0x440e /* T440-LP-CR */
+#define PCI_PRODUCT_CHELSIO_T580_DBG 0x5400 /* T580-dbg */
+#define PCI_PRODUCT_CHELSIO_T520_CR 0x5401 /* T520-CR */
+#define PCI_PRODUCT_CHELSIO_T522_CR 0x5402 /* T522-CR */
+#define PCI_PRODUCT_CHELSIO_T540_CR 0x5403 /* T540-CR */
+#define PCI_PRODUCT_CHELSIO_T520_SO 0x5407 /* T520-SO */
+#define PCI_PRODUCT_CHELSIO_T520_BT 0x5409 /* T520-BT */
+#define PCI_PRODUCT_CHELSIO_T504_BT 0x540a /* T504-BT */
+#define PCI_PRODUCT_CHELSIO_T580_CR 0x540d /* T580-CR */
+#define PCI_PRODUCT_CHELSIO_T540_LP_CR 0x540e /* T540-LP-CR */
+#define PCI_PRODUCT_CHELSIO_T580_LP_CR 0x5410 /* T580-LP-CR */
+#define PCI_PRODUCT_CHELSIO_T520_LL_CR 0x5411 /* T520-LL-CR */
+#define PCI_PRODUCT_CHELSIO_T560_CR 0x5412 /* T560-CR */
+#define PCI_PRODUCT_CHELSIO_T580_LP_SO_CR 0x5414 /* T580-LP-SO-CR */
+#define PCI_PRODUCT_CHELSIO_T502_BT 0x5415 /* T502-BT */
+#define PCI_PRODUCT_CHELSIO_T6_DBG_25 0x6400 /* T6-DBG-25 */
+#define PCI_PRODUCT_CHELSIO_T6225_CR 0x6401 /* T6225-CR */
+#define PCI_PRODUCT_CHELSIO_T6225_SO_CR 0x6402 /* T6225-SO-CR */
+#define PCI_PRODUCT_CHELSIO_T6425_CR 0x6403 /* T6425-CR */
+#define PCI_PRODUCT_CHELSIO_T6425_SO_CR 0x6404 /* T6425-SO-CR */
+#define PCI_PRODUCT_CHELSIO_T6225_OCP_SO 0x6405 /* T6225-OCP-SO */
+#define PCI_PRODUCT_CHELSIO_T62100_OCP_SO 0x6406 /* T62100-OCP-SO */
+#define PCI_PRODUCT_CHELSIO_T62100_LP_CR 0x6407 /* T62100-LP-CR */
+#define PCI_PRODUCT_CHELSIO_T62100_SO_CR 0x6408 /* T62100-SO-CR */
+#define PCI_PRODUCT_CHELSIO_T6210_BT 0x6409 /* T6210-BT */
+#define PCI_PRODUCT_CHELSIO_T62100_CR 0x640d /* T62100-CR */
+#define PCI_PRODUCT_CHELSIO_T6_DBG_100 0x6410 /* T6-DBG-100 */
+#define PCI_PRODUCT_CHELSIO_T6225_LL_CR 0x6411 /* T6225-LL-CR */
+#define PCI_PRODUCT_CHELSIO_T61100_OCP_SO 0x6414 /* T61100-OCP-SO */
+#define PCI_PRODUCT_CHELSIO_T6201_BT 0x6415 /* T6201-BT */
+#define PCI_PRODUCT_CHELSIO_T6225_80 0x6480 /* T6225 80 */
+#define PCI_PRODUCT_CHELSIO_T62100_81 0x6481 /* T62100 81 */
+#define PCI_PRODUCT_CHELSIO_T62100_84 0x6484 /* T62100 84 */
+#define PCI_PRODUCT_CHELSIO_T4_FPGA 0xa000 /* Terminator 4 FPGA */
+#define PCI_PRODUCT_CHELSIO_T5_FPGA 0xb000 /* Terminator 5 FPGA */
+#define PCI_PRODUCT_CHELSIO_T6_FPGA 0xc006 /* Terminator 6 FPGA */
/* Chips and Technologies products */
#define PCI_PRODUCT_CHIPS_64310 0x00b8 /* 64310 */
@@ -2446,6 +2500,7 @@
#define PCI_PRODUCT_MARVELL_YUKON_8038 0x4352 /* Yukon 88E8038 */
#define PCI_PRODUCT_MARVELL_YUKON_8039 0x4353 /* Yukon 88E8039 */
#define PCI_PRODUCT_MARVELL_YUKON_8040 0x4354 /* Yukon 88E8040 */
+#define PCI_PRODUCT_MARVELL_YUKON_8040T 0x4355 /* Yukon 88E8040T */
#define PCI_PRODUCT_MARVELL_YUKON_C033 0x4356 /* Yukon 88EC033 */
#define PCI_PRODUCT_MARVELL_YUKON_8052 0x4360 /* Yukon 88E8052 */
#define PCI_PRODUCT_MARVELL_YUKON_8050 0x4361 /* Yukon 88E8050 */
@@ -2702,29 +2757,29 @@
#define PCI_PRODUCT_INTEL_CORE_PCIE_2 0x0049 /* Core PCIe Root Port */
#define PCI_PRODUCT_INTEL_IRONLAKE_MA_HB 0x0062 /* Iron Lake Host Bridge */
#define PCI_PRODUCT_INTEL_IRONLAKE_MC2_HB 0x006a /* Iron Lake Host Bridge */
-#define PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1 0x0082 /* Centrino Advanced-N 6205 */
+#define PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1 0x0082 /* Centrino Advanced-N 6205 WiFi */
#define PCI_PRODUCT_INTEL_WIFI_LINK_1000_1 0x0083 /* WiFi Link 1000 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_1000_2 0x0084 /* WiFi Link 1000 */
-#define PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2 0x0085 /* Centrino Advanced-N 6205 */
-#define PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1 0x0087 /* Centrino Advanced-N 6250 */
-#define PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2 0x0089 /* Centrino Advanced-N 6250 */
+#define PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2 0x0085 /* Centrino Advanced-N 6205 WiFi */
+#define PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1 0x0087 /* Centrino Advanced-N 6250 WiFi */
+#define PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2 0x0089 /* Centrino Advanced-N 6250 WiFi */
#define PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 0x008a /* Centrino Wireless-N 1030 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 0x008b /* Centrino Wireless-N 1030 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 0x0090 /* Centrino Advanced-N 6230 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 0x0091 /* Centrino Advanced-N 6230 */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_HB 0x0100 /* Sandy Bridge Host Bridge */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_PCIE 0x0101 /* Sandy Bridge PCIe Root port */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD 0x0102 /* Sandy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Sandy Bridge Host Bridge */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_PCIE_1 0x0105 /* Sandy Bridge PCIe Root port */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD 0x0106 /* Sandy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Sandy Bridge Host Bridge */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_PCIE_2 0x0109 /* Sandy Bridge PCIe Root port */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_S_IGD 0x010A /* Sandy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_1 0x0112 /* Sandy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_1 0x0116 /* Sandy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_2 0x0122 /* Sandy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_2 0x0126 /* Sandy Bridge Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_HB 0x0100 /* Sandy Bridge (desktop) Host Bridge */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_PCIE 0x0101 /* Sandy Bridge (desktop) PCIe Root port */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD 0x0102 /* Sandy Bridge (desktop) GI1 Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Sandy Bridge (mobile) Host Bridge */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_PCIE_1 0x0105 /* Sandy Bridge (mobile) PCIe Root port */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD 0x0106 /* Sandy Bridge (mobile) GT1 Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Sandy Bridge (server) Host Bridge */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_PCIE_2 0x0109 /* Sandy Bridge (server) PCIe Root port */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_S_IGD 0x010A /* Sandy Bridge (server) GT1 Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_1 0x0112 /* Sandy Bridge GT2 Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_1 0x0116 /* Sandy Bridge (mobile) GT2 Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_2 0x0122 /* Sandy Bridge (desktop) GT2+ Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_2 0x0126 /* Sandy Bridge (mobile) GT2+ Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_IVYBRIDGE_HB 0x0150 /* Ivy Bridge Host Bridge */
#define PCI_PRODUCT_INTEL_IVYBRIDGE_PCIE 0x0151 /* Ivy Bridge PCI Express Root Port */
#define PCI_PRODUCT_INTEL_IVYBRIDGE_IGD 0x0152 /* Ivy Bridge Integrated Graphics Device */
@@ -2847,6 +2902,96 @@
#define PCI_PRODUCT_INTEL_S1200_S1220 0x0c72 /* Atom S1220 Internal */
#define PCI_PRODUCT_INTEL_S1200_S1240 0x0c73 /* Atom S1240 Internal */
#define PCI_PRODUCT_INTEL_S1200_S1260 0x0c75 /* Atom S1260 Internal */
+#define PCI_PRODUCT_INTEL_E5V2_DMI2 0x0e00 /* E5 v2 DMI2 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_1 0x0e01 /* E5 v2 PCIe x4 (DMI2 Mode) */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_2 0x0e02 /* E5 v2 PCIe */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_3 0x0e03 /* E5 v2 PCIe */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_4 0x0e04 /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_5 0x0e05 /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_6 0x0e06 /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_7 0x0e07 /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_8 0x0e08 /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_9 0x0e09 /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_10 0x0e0a /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_11 0x0e0b /* E5 v2 PCIe x16, x8 or x4 */
+#define PCI_PRODUCT_INTEL_E5V2_R2PCIE 0x0e1d /* E5 v2 R2PCIE */
+#define PCI_PRODUCT_INTEL_E5V2_UBOX_1 0x0e1e /* E5 v2 UBOX */
+#define PCI_PRODUCT_INTEL_E5V2_UBOX_2 0x0e1f /* E5 v2 UBOX */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_0 0x0e20 /* E5 v2 I/OAT DMA Channel 0 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_1 0x0e21 /* E5 v2 I/OAT DMA Channel 1 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_2 0x0e22 /* E5 v2 I/OAT DMA Channel 2 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_3 0x0e23 /* E5 v2 I/OAT DMA Channel 3 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_4 0x0e24 /* E5 v2 I/OAT DMA Channel 4 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_5 0x0e25 /* E5 v2 I/OAT DMA Channel 5 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_6 0x0e26 /* E5 v2 I/OAT DMA Channel 6 */
+#define PCI_PRODUCT_INTEL_E5V2_IOAT_7 0x0e27 /* E5 v2 I/OAT DMA Channel 7 */
+#define PCI_PRODUCT_INTEL_E5V2_ADDRMAP 0x0e28 /* E5 v2 Address Map */
+#define PCI_PRODUCT_INTEL_E5V2_HOTPLUG 0x0e29 /* E5 v2 Hot-Plug */
+#define PCI_PRODUCT_INTEL_E5V2_IIO_RAS 0x0e2a /* E5 v2 IIO RAS */
+#define PCI_PRODUCT_INTEL_E5V2_IOAPIC 0x0e2c /* E5 v2 I/O APIC */
+#define PCI_PRODUCT_INTEL_E5_IOAT_RAID_1 0x3c2e /* E5 I/OAT DMA (RAID 5/6) */
+#define PCI_PRODUCT_INTEL_E5_IOAT_RAID_2 0x3c2f /* E5 I/OAT DMA (RAID 5/6) */
+#define PCI_PRODUCT_INTEL_E5V2_HA_2 0x0e30 /* E5 v2 Home Agent */
+#define PCI_PRODUCT_INTEL_E5V2_PCIE_PM_1 0x0e34 /* E5 v2 PCIe Performance Monitor */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_PM_1 0x0e36 /* E5 v2 QPI Performance Monitor */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_PM_2 0x0e37 /* E5 v2 QPI Performance Monitor */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_1 0x0e41 /* E5 v2 QPI */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_RAS 0x0e71 /* E5 v2 IMC RAS */
+#define PCI_PRODUCT_INTEL_E5V2_UBOX_3 0x0e7d /* E5 v2 UBOX */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_L_0 0x0e80 /* E5 v2 QPI Link 0 */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_2 0x0e81 /* E5 v2 QPI */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_L_0_1 0x0e83 /* E5 v2 QPI Link Reut 0 */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_L_0_2 0x0e84 /* E5 v2 QPI Link Reut 0 */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_L_1 0x0e90 /* E5 v2 QPI Link 1 */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_L_1_1 0x0e93 /* E5 v2 QPI Link Reut 1 */
+#define PCI_PRODUCT_INTEL_E5V2_QPI_L_1_2 0x0e94 /* E5 v2 QPI Link Reut 1 */
+#define PCI_PRODUCT_INTEL_E5V2_HA_1 0x0ea0 /* E5 v2 Home Agent */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_TA 0x0ea8 /* E5 v2 IMC TA */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_TAD_1 0x0eaa /* E5 v2 IMC TAD */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_TAD_2 0x0eab /* E5 v2 IMC TAD */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_TAD_3 0x0eac /* E5 v2 IMC TAD */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_TAD_4 0x0ead /* E5 v2 IMC TAD */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_THERMAL_1 0x0eb0 /* E5 v2 IMC Thermal */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_THERMAL_2 0x0eb1 /* E5 v2 IMC Thermal */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_ERR_1 0x0eb2 /* E5 v2 IMC Error */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_ERR_2 0x0eb3 /* E5 v2 IMC Error */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_THERMAL_3 0x0eb4 /* E5 v2 IMC Thermal */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_THERMAL_4 0x0eb5 /* E5 v2 IMC Thermal */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_ERR_3 0x0eb6 /* E5 v2 IMC Error */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_ERR_4 0x0eb7 /* E5 v2 IMC Error */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_1 0x0eba /* E5 v2 IMC DDRIO 0,1,2,3 Multicast */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_2 0x0ebb /* E5 v2 IMC DDRIO 0,1,2,3 Multicast */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_3 0x0ebc /* E5 v2 IMC DDRIO 0 & 1 */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_4 0x0ebd /* E5 v2 IMC DDRIO 0 & 1 */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_5 0x0ebe /* E5 v2 IMC DDRIO 0,1 Multicast */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_6 0x0ebf /* E5 v2 IMC DDRIO 0,1 Multicast */
+#define PCI_PRODUCT_INTEL_E5V2_PCU_0 0x0ec0 /* E5 v2 PCU */
+#define PCI_PRODUCT_INTEL_E5V2_PCU_1 0x0ec1 /* E5 v2 PCU */
+#define PCI_PRODUCT_INTEL_E5V2_PCU_2 0x0ec2 /* E5 v2 PCU */
+#define PCI_PRODUCT_INTEL_E5V2_PCU_3 0x0ec3 /* E5 v2 PCU */
+#define PCI_PRODUCT_INTEL_E5V2_PCU_4 0x0ec4 /* E5 v2 PCU */
+#define PCI_PRODUCT_INTEL_E5V2_SAD_1 0x0ec8 /* E5 v2 SAD */
+#define PCI_PRODUCT_INTEL_E5V2_BROADCAST_1 0x0ec9 /* E5 v2 Broadcast */
+#define PCI_PRODUCT_INTEL_E5V2_BROADCAST_2 0x0eca /* E5 v2 Broadcast */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_7 0x0ed8 /* E5 v2 IMC DDRIO 2 & 3 */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_8 0x0ed9 /* E5 v2 IMC DDRIO 2 & 3 */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_9 0x0eda /* E5 v2 IMC DDRIO 2 & 3 */
+#define PCI_PRODUCT_INTEL_E5V2_IMC_DDRIO_10 0x0edb /* E5 v2 IMC DDRIO 2 & 3 */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_1 0x0ee0 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_2 0x0ee1 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_3 0x0ee2 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_4 0x0ee3 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_5 0x0ee4 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_6 0x0ee5 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_7 0x0ee6 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_8 0x0ee7 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_9 0x0ee8 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_10 0x0ee9 /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_11 0x0eea /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_12 0x0eeb /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_13 0x0eec /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_14 0x0eed /* E5 v2 Unicast */
+#define PCI_PRODUCT_INTEL_E5V2_UNICAST_15 0x0eee /* E5 v2 Unicast */
#define PCI_PRODUCT_INTEL_BAYTRAIL_HB 0x0f00 /* Bay Trail Processor Transaction Router */
#define PCI_PRODUCT_INTEL_BAYTRAIL_HDA 0x0f04 /* Bay Trail HD Audio */
#define PCI_PRODUCT_INTEL_BAYTRAIL_SIO2_DMA 0x0f06 /* Bay Trail Serial IO (DMA) */
@@ -2856,7 +3001,7 @@
#define PCI_PRODUCT_INTEL_BAYTRAIL_SIO2_UART2 0x0f0c /* Bay Trail Serial IO (HSUART) */
#define PCI_PRODUCT_INTEL_BAYTRAIL_SIO2_SPI 0x0f0e /* Bay Trail Serial IO (SPI) */
#define PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB 0x0f12 /* Bay Trail PCU SMBus */
-#define PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC 0x0f14 /* Bay Trail Storage Control Cluster(MMC) */
+#define PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC 0x0f14 /* Bay Trail Storage Control Cluster(eMMC) */
#define PCI_PRODUCT_INTEL_BAYTRAIL_SCC_SDIO 0x0f15 /* Bay Trail Storage Control Cluster(SDIO) */
#define PCI_PRODUCT_INTEL_BAYTRAIL_SCC 0x0f16 /* Bay Trail Storage Control Cluster(SD) */
#define PCI_PRODUCT_INTEL_BAYTRAIL_TXE 0x0f18 /* Bay Trail Trusted Execution Engine */
@@ -2883,6 +3028,7 @@
#define PCI_PRODUCT_INTEL_BAYTRAIL_PCIE_2 0x0f4a /* Bay Trail PCIE Root Port */
#define PCI_PRODUCT_INTEL_BAYTRAIL_PCIE_3 0x0f4c /* Bay Trail PCIE Root Port */
#define PCI_PRODUCT_INTEL_BAYTRAIL_PCIE_4 0x0f4e /* Bay Trail PCIE Root Port */
+#define PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC2 0x0f50 /* Bay Trail Storage Control Cluster(eMMC 4.5) */
#define PCI_PRODUCT_INTEL_82542 0x1000 /* i82542 Gigabit Ethernet */
#define PCI_PRODUCT_INTEL_82543GC_FIBER 0x1001 /* i82453GC 1000baseX Ethernet */
#define PCI_PRODUCT_INTEL_MODEM56 0x1002 /* 56k Modem */
@@ -3143,6 +3289,11 @@
#define PCI_PRODUCT_INTEL_XL710_QSFP_B 0x1584 /* XL710 40GbE QSFP+ */
#define PCI_PRODUCT_INTEL_XL710_QSFP_C 0x1585 /* XL710 40GbE QSFP+ */
#define PCI_PRODUCT_INTEL_X710_10G_T 0x1586 /* X710 10GBaseT Ethernet */
+#define PCI_PRODUCT_INTEL_XL710_20G_BP_1 0x1587 /* XL710 20GbE Backplane */
+#define PCI_PRODUCT_INTEL_XL710_20G_BP_2 0x1588 /* XL710 20GbE Backplane */
+#define PCI_PRODUCT_INTEL_X710_T4_10G 0x1589 /* X710-T4 10GbaseT */
+#define PCI_PRODUCT_INTEL_XXV710_25G_BP 0x158a /* XXV710 25GbE Backplane */
+#define PCI_PRODUCT_INTEL_XXV710_25G_SFP28 0x158b /* XXV710 SFP28 */
#define PCI_PRODUCT_INTEL_I218_LM2 0x15a0 /* I218-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_I218_V2 0x15a1 /* I218-V Ethernet Connection */
#define PCI_PRODUCT_INTEL_I218_LM3 0x15a2 /* I218-LM Ethernet Connection */
@@ -3160,12 +3311,12 @@
#define PCI_PRODUCT_INTEL_I219_LM3 0x15b9 /* I219-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_C3K_X553_KRKX 0x15c2 /* C3000 X553 Backplane (KR/KX 10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_KX_25G 0x15c3 /* C3000 X553 Backplane (KX 2.5G) */
-#define PCI_PRODUCT_INTEL_C3K_X553_SFI_SFP 0x15c4 /* C3000 X553 10G SFP+ */
+#define PCI_PRODUCT_INTEL_C3K_X553_SFI_SFP 0x15c4 /* C3000 X553 10G SFP+ (SFI) */
#define PCI_PRODUCT_INTEL_C3K_X553_VF 0x15c5 /* C3000 X553 VF */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_BP 0x15c6 /* C3000 X553 1GbE SGMII Backplane (10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_BP_L 0x15c7 /* C3000 X553 1GbE SGMII Backplane (non-10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_10G_T 0x15c8 /* C3000 X553 10GBASE-T (X557) */
-#define PCI_PRODUCT_INTEL_C3K_X553_KR_SFP 0x15ce /* C3000 X553 10G SFP+ */
+#define PCI_PRODUCT_INTEL_C3K_X553_KR_SFP 0x15ce /* C3000 X553 10G SFP+ (KR) */
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