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Re: use of MI "pcu" code for x86 FPU, allocate FPU context dynamically

On Mon, 9 Sep 2013 22:11:34 +0100
David Laight <david%l8s.co.uk@localhost> wrote:
> I looked a bit at AVX support and was dismayed at the unnecessary
> differences between i386 and amd64.
> It seems best to merge those to some extent - if only the .h files
> for common structures - before embarking on any more changes.

The structures are already different for SSE2 (8 vs 16 regs), this
multiplies for AVX and future extensions. There is not much potential
for code line reduction on the structure side. What stays the same is
the algorithms, for keeping track which CPU has the FP context of
which LWP, and this is what the pcu code provides.

> 1) i386 core dumps seem to only have i387 support.
> [...]
> 2) The whole way that core dumps are generated needs to be changed
>    in order to not need on-stack copies of the FP state.
>    I think there are currently two copies, dump the AVX registers
>    and you'll blow the kernel stack.

Agreed that there are deficiencies, but my changes don't touch this
at all. I'm not even sure if it makes sense to provide AVX for 32-bit
i386. It would mean to blow up the uarea by a page, or to do dynamic
allocation. Both could be harmful to low-end embedded uses.

> Also make sure that anything you do is compatible with the optimised
> FP resgister saving of the newer intel cpus.
> I didn't quite grok all of it, but I think it is carefully arranged
> so that the FP save instruction knows which registers need saving
> (or restoring) saving all the memory cycles when no regsisters
> in one of the blocks has been modified.

Yes, this works for modern CPUs (so modern that noone would run a 32bit
OS on it). I didn't find a way to find out how much memory is needed
in advance -- this means that the maximum reported by CPUID would
have to be allocated even if only basic SSE2 registers are needed.

best regards

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