Re: sysutils/xenkernel33

["Sam Fourman Jr." <sfourman%gmail.com@localhost>]

On Thu, Jul 1, 2010 at 4:23 AM, Manuel Bouyer 
<bouyer%antioche.eu.org@localhost> wrote:
> On Wed, Jun 30, 2010 at 07:22:54PM -0500, Sam Fourman Jr. wrote:
>> [...]
>> /usr/pkgsrc/sysutils/xenkernel33/work/xen-3.3.2/xen/include/asm/processor.h:174:
>> error: requested alignment is not a constant
>
> this is:
> struct cpuinfo_x86 {
>  [...]
> } __cacheline_aligned;
>
> and I guess __cacheline_aligned is:
>
> ./xen/include/xen/cache.h:#define __cacheline_aligned 
> __attribute__((__aligned__(SMP_CACHE_BYTES)))
>
> SMP_CACHE_BYTES would be:
> ./xen/include/asm-x86/cache.h:#define L1_CACHE_SHIFT   
>  (CONFIG_X86_L1_CACHE_SHIFT)
> ./xen/include/asm-x86/cache.h:#define L1_CACHE_BYTES    (1 << L1_CACHE_SHIFT)
>
> ./xen/include/xen/cache.h:#define SMP_CACHE_BYTES L1_CACHE_BYTES
>
> ./xen/include/asm-x86/config.h:#define CONFIG_X86_L1_CACHE_SHIFT 7
>
> Can you check that your asm-x86/config.h has the same value, or that
> it's not defined at some other place ?
>

/* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
#define CONFIG_X86_L1_CACHE_SHIFT 7


-- 

Sam Fourman Jr.
Fourman Networks
http://www.fourmannetworks.com