On Wed, Mar 15, 2006 at 04:51:55PM -0500, Jed Davis wrote:
> Manuel Bouyer <bouyer@antioche.eu.org> writes:
> 
> > It doesn't look bad, but are you sure the sfence and mfence instructions
> > are needed, and exists on older P6 CPUs ? If I understood it right and
> > remmeber properly these are only needed when using SSE2 instructions (but
> > I may either have misunderstood or misremember)
> 
> Further reading (including an Intel manual and Xen's (Linux-derived)
> macros) suggest that I vastly overestimated the support for the fence
> insns, and the locked memory reference thing should remain.
> 
> As for sfence: it's part of SSE, and according to Intel needed only if
> memory is explicitly mapped as write-combining or accessed with a
> special "non-temporal" store insn.  According to comments in Linux,
> there exist non-Intel clones that do out-of-order store, and a
> non-noop sfence is needed there, but they don't enable it by default.
> It's lfence and mfence that are part of SSE2.
> 
> So, here's the patch without that mistake.

OK, looks good. Thanks 

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
     NetBSD: 26 ans d'experience feront toujours la difference
--