On Wed, Mar 15, 2006 at 04:51:55PM -0500, Jed Davis wrote:
> 
> As for sfence: it's part of SSE, and according to Intel needed only if
> memory is explicitly mapped as write-combining or accessed with a
> special "non-temporal" store insn.  According to comments in Linux,
> there exist non-Intel clones that do out-of-order store, and a
> non-noop sfence is needed there, but they don't enable it by default.
> It's lfence and mfence that are part of SSE2.

Do we need to worry about BIOSes leaving video or other device memory
mapped as write-combining?

Thor