Re: syncing the GCC vax port, atomic issue

[coypu%sdf.org@localhost]

On Fri, Sep 20, 2019 at 03:45:46PM -0600, Jeff Law wrote:
> Conditional branching patterns must support the label_ref and pc
> operands in either position.  Everything else I've seen on this thread
> is just working around that broken aspect of the builtins.md file.
> 
> 
> (define_insn "jbbssiqi"
>   [(parallel
>     [(set (pc)
> 	  (if_then_else
> 	    (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "g")
> 				 (const_int 1)
> 				 (match_operand:SI 1 "general_operand" "nrm"))
> 		(const_int 0))
> 	    (label_ref (match_operand 2 "" ""))
> 	    (pc)))
>      (set (zero_extract:SI (match_operand:QI 3 "memory_operand" "+0")
> 			   (const_int 1)
> 			   (match_dup 1))
> 	  (const_int 1))])]
>   ""
>   "jbssi %1,%0,%l2")
> 
> Note the position of the (label_ref ...) and (pc) operand.  You have to
> have a pattern where they are reversed as well.
> 
> As an example look at the branch and branch_reversed patterns in vax.md
> 
> jeff

Hi Jeff,

Thanks for the advice.
Introducing the reversed jbb* patterns doesn't seem to help with the
original issue. It crashes building libatomic.
I've attempted the following diff, as suggested by Maciej W. Rozycki.

(This isn't failing in the latest GCC because it doesn't include
vax/builtins.md at all)

> Ouch, there are no reversed interlocked branch instructions in the VAX
> ISA, so these would have to branch around a jump.
... https://gcc.gnu.org/ml/gcc/2018-04/msg00073.html

Is it the intended diff? did I get something wrong?

diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md
index 2261467..db8ddc40 100644
--- a/gcc/config/vax/builtins.md
+++ b/gcc/config/vax/builtins.md
@@ -90,6 +90,24 @@
   ""
   "jbssi %1,%0,%l2")
 
+(define_insn "jbbssiqi_reversed"
+  [(parallel
+    [(set (pc)
+	  (if_then_else
+	    (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "g")
+				 (const_int 1)
+				 (match_operand:SI 1 "general_operand" "nrm"))
+		(const_int 0))
+	    (pc)
+	    (label_ref (match_operand 2 "" ""))))
+     (set (zero_extract:SI (match_operand:QI 3 "memory_operand" "+0")
+			   (const_int 1)
+			   (match_dup 1))
+	  (const_int 1))])]
+  ""
+  "jbssi %1,%0,0f\;jbr %l2\;0:")
+
+
 (define_insn "jbbssihi"
   [(parallel
     [(set (pc)
@@ -107,6 +125,24 @@
   ""
   "jbssi %1,%0,%l2")
 
+(define_insn "jbbssihi_reversed"
+  [(parallel
+    [(set (pc)
+          (if_then_else
+            (ne (zero_extract:SI (match_operand:HI 0 "memory_operand" "Q")
+                                 (const_int 1)
+                                 (match_operand:SI 1 "general_operand" "nrm"))
+                (const_int 0))
+            (pc)
+            (label_ref (match_operand 2 "" ""))))
+     (set (zero_extract:SI (match_operand:HI 3 "memory_operand" "+0")
+                           (const_int 1)
+                           (match_dup 1))
+          (const_int 1))])]
+  ""
+  "jbssi %1,%0,0f\;jbr %l2\;0:")
+
+
 (define_insn "jbbssisi"
   [(parallel
     [(set (pc)
@@ -125,6 +161,25 @@
   "jbssi %1,%0,%l2")
 
 
+(define_insn "*jbbssisi_reversed"
+  [(parallel
+    [(set (pc)
+	  (if_then_else
+	    (ne (zero_extract:SI (match_operand:SI 0 "memory_operand" "Q")
+				 (const_int 1)
+				 (match_operand:SI 1 "general_operand" "nrm"))
+		(const_int 0))
+	    (pc)
+	    (label_ref (match_operand 2 "" ""))))
+     (set (zero_extract:SI (match_operand:SI 3 "memory_operand" "+0")
+			   (const_int 1)
+			   (match_dup 1))
+	  (const_int 1))])]
+  ""
+  "jbssi %1,%0,0f\; jbr %l2\;0:")
+
+
+
 (define_expand "sync_lock_release<mode>"
   [(set (match_operand:VAXint 0 "memory_operand" "+m")
 	(unspec:VAXint [(match_operand:VAXint 1 "const_int_operand" "n")
@@ -162,6 +217,23 @@
   ""
   "jbcci %1,%0,%l2")
 
+(define_insn "jbbcciqi_reversed"
+  [(parallel
+    [(set (pc)
+	  (if_then_else
+	    (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "g")
+				 (const_int 1)
+				 (match_operand:SI 1 "general_operand" "nrm"))
+		(const_int 0))
+	    (pc)
+	    (label_ref (match_operand 2 "" ""))))
+     (set (zero_extract:SI (match_operand:QI 3 "memory_operand" "+0")
+			   (const_int 1)
+			   (match_dup 1))
+	  (const_int 0))])]
+  ""
+  "jbcci %1,%0,0f\; jbr %l2\;0:")
+
 (define_insn "jbbccihi"
   [(parallel
     [(set (pc)
@@ -179,6 +251,24 @@
   ""
   "jbcci %1,%0,%l2")
 
+
+(define_insn "jbbccihi_reversed"
+  [(parallel
+    [(set (pc)
+	  (if_then_else
+	    (eq (zero_extract:SI (match_operand:HI 0 "memory_operand" "Q")
+				 (const_int 1)
+				 (match_operand:SI 1 "general_operand" "nrm"))
+		(const_int 0))
+	    (pc)
+	    (label_ref (match_operand 2 "" ""))))
+     (set (zero_extract:SI (match_operand:HI 3 "memory_operand" "+0")
+			   (const_int 1)
+			   (match_dup 1))
+	  (const_int 0))])]
+  ""
+  "jbcci %1,%0,0f\; jbr %l2\;0:")
+
 (define_insn "jbbccisi"
   [(parallel
     [(set (pc)
@@ -195,3 +285,21 @@
 	  (const_int 0))])]
   ""
   "jbcci %1,%0,%l2")
+
+(define_insn "jbbccisi_reversed"
+  [(parallel
+    [(set (pc)
+          (if_then_else
+            (eq (zero_extract:SI (match_operand:SI 0 "memory_operand" "Q")
+                                 (const_int 1)
+                                 (match_operand:SI 1 "general_operand" "nrm"))
+                (const_int 0))
+            (pc)
+            (label_ref (match_operand 2 "" ""))))
+     (set (zero_extract:SI (match_operand:SI 3 "memory_operand" "+0")
+                           (const_int 1)
+                           (match_dup 1))
+          (const_int 0))])]
+  ""
+  "jbssi %1,%0,0f\;jbr %l2\;0:")
+