On Wed, 2 Apr 2008, raymond.meyer%rambler.ru@localhost wrote:
When a TLB miss occurs on UltraSPARC-IIi, it issues a trap to system software,
which fills the TLB. Other processors have hardware support to automatically
service TLB misses.
My question is, why UltraSPARC-IIi does not provide such hardware support? Is
it because to reduce the cost of manufacture? Or are there any advantages of
handling TLB misses in software?
Most CISC chips do H/W page table walks. Most RISC chips don't. It comes
down to whether you think the hardware guys or the software guys can lay
out a more efficient page table. (Like on Linux all MMUs are Intel
MMUs...)
Eduardo