Hi,

I'm aware that SMP on Sparc64 is currently "not there", but still I'd 
really love to see it happen...

I have an Ultra60 with 2x 450 MHz here, and this is what happens at bootup
of a kernel with MULTIPROCESSOR set:

NetBSD 3.99.7 (SCOTTY-IPSEC.MP) #0: Wed Jul 20 00:40:57 CEST 2005
        gert@epsilon:/home/sparc64.current/obj/home/src-current/sys/arch/sparc64/compile/SCOTTY-IPSEC.MP
total memory = 2048 MB
avail memory = 2000 MB
mainbus0 (root): SUNW,Ultra-60: hostid 80ced299
cpu0 at mainbus0: SUNW,UltraSPARC-II @ 450.053 MHz, version 0 FPU
cpu0: 32K instruction (32 b/l), 16K data (32 b/l), 4096K external (64 b/l)
cpu1 at mainbus0: SUNW,UltraSPARC-II @ 450.053 MHz, version 0 FPU
cpu1: 32K instruction (32 b/l), 16K data (32 b/l), 4096K external (64 b/l)
psycho0 at mainbus0 addr 0xfffb4000
...

- looks not too bad :) - but then:

...
root on sd0a dumps on sd0b
root file system type: ffs
cpu0: booting secondary processors:
cpu2 now spinning idle (waited 1 iterations)

text_access_fault: pc=1c09c90 va=1c08000
ffb0: ffbfb_unblank
kernel trap 64: +fast instruction access MMU miss
cpu0 paused.
Stopped in pid 1.1 (init) at
SIR Reset

Watchdog Reset
Externally Initiated Reset
{2} ok 


- not good.

Is there anything I can do to help trace this, or get this implemented?

I have no clue at all about Sparc64 assembler or kernel-level SMP issues,
but I could arrange to put this machine somewhere where people can 
remotely access the serial console and run tests... and of course I'm
willing to run test kernels and experiment :-) 

gert

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Gert Doering - Munich, Germany                             gert@greenie.muc.de
fax: +49-89-35655025                        gert@net.informatik.tu-muenchen.de