Re: SBus driver & burst (>32 bits) accesses

[Romain Dolbeau <romain%dolbeau.org@localhost>]

Le lun. 14 déc. 2020 à 18:53, Eduardo Horvath <eeh%netbsd.org@localhost> a écrit :
> That's because the firmware is presumabley FCode and is interpreted one
> byte at a time.

It is FCode, but from the specs it should theoretically be OK to
decline the 8 bits transfers and force the system to do bus sizing and
go to 32 bits (IEEE-1496 section 5.4.6)...
I would have expected a newer SPARCstation like the SS20 (which is
what I'm testing my board in) to try 32 bits for faster transfers
before falling back to 8 bits.
But I guess as you only read it once at POST time, it doesn't really
matter. That's what I get for trying to design new hardware for a 25+
years workstation :-)

> I believe burst mode only works during DMA

It would seem logical. From the CPU, load/store will only access up to
32 bits in v8 (64 bits in v9). It probably can't do anything larger
without dedicated hardware; i.e. DMA.
I kind of hoped there would be a DMA available somewhere, but as far
as I can see the only one in the system is the LSI 64854 for the ESP
and LE devices, and I don't think I can coerce it into sending data
from memory to my hardware... I need my own DMA engine :-/

> I assume you're on a SPARC here.

Yes, I should have said so explicitly; I'm posting to 'port-sparc' so
it's a reasonable assumption :-)

> On SPARC the coherency space goes only as far as the external cache.
> Since the SBus space is uncached, the CPU will only do single bus
> transactions.  To use burst mode you will need to use DMA driven by the
> device and probably also need to make sure the IOMMU entries are set up to
> use the SBus controller's streaming cache.  This may only work on
> UltraSPARC machines since I don't think the SBus controllers on any of the
> 32-bit SPARCs have streaming caches.

Even the SPARCstation 1 is documented as being able to do 16-byte
bursts (and only those), while the later specifications (Sun's B0 and
IEEE-1496) enable up to 64 bytes bursts in 32 bits (16 words) and 128
using Extended Transfers (64 bits mode).

I though Extended Transfers were only available on v9 hardware
(ultra), but the PROM from the SS20 report supporting them if I
understand the NetBSD code correctly (when looking up the devices's
parent's 'sc_burst'); it reports being able to do all bursts
(1/2/4/8/16 words/doublewords).

Now I need to figure out how to implement a SBus DMA bus master in my
FPGA... and then maybe try for Extended Transfers as well just to see
if they really work :-)

Thanks & cordially,

-- 
Romain Dolbeau