Re: partially working SMP again

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

> An easy check is to add this at the end of pmap_bootstrap4m:
> 
>         if (curcpu()->ci_self != cpus[0])
>                 panic("cpuinfo inconsistent");

This test fails on my SS20MP.

Using PMAP_NC on remapping cpuinfo_data and removing SRMMU_PG_C
on CPUINFO_VA mappings seems to fix the inconsistency (alias problem?),
though it still fails later:

---
Booting netbsd.mp2
3648012+108384+267888 [243472+229434]=0x45a2b8
OBP version 3, revision 2.25 (plugin rev 2)
going to pmap_kenter_pa(va=0xf045f000, pa=0x402000)
setting cpus self reference
set cpu0 ci_self address: 0xf045f000
set cpu1 ci_self address: 0xf0460000
set cpu2 ci_self address: 0xf0461000
set cpu3 ci_self address: 0xf0462000
pmap_bootstrap4m done
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 5.99.12 (DEBUG) #11: Fri May 29 01:17:41 JST 2009
        tsutsui@mirage:/usr/src/sys/arch/sparc/compile/DEBUG
total memory = 127 MB
avail memory = 120 MB
bootpath: /iommu@f,e0000000/sbus@f,e0001000/espdma@f,400000/esp@f,800000/sd@1,0
mainbus0 (root): SUNW,SPARCstation-20: hostid 727aaa0a
cpu0 at mainbus0: mid 8: RT620/625 @ 150 MHz, on-chip FPU
cpu0: 512K byte write-back, 32 bytes/line, sw flush: 
cpu1 at mainbus0: mid 9: RT620/625 @ 150 MHz, on-chip FPU
cpu1: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu2 at mainbus0: mid 10: RT620/625 @ 150 MHz, on-chip FPU
cpu2: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu3 at mainbus0: mid 11data fault: pc=0xf004e1c8 addr=0x1d4 
sfsr=0x126<PERR=0x0,LVL=0x1,AT=0x1,FT=0x1,FAV,OW>
data fault: pc=0xf024a128 addr=0x1d4 
sfsr=0x126<PERR=0x0,LVL=0x1,AT=0x1,FT=0x1,FAV,OW>
data fault: pc=0xf024a128 addr=0x1d4 
sfsr=0x126<PERR=0x0,LVL=0x1,AT=0x1,FT=0x1,FAV,OW>
data fault: pc=0xf024a128 addr=0x1d4 
sfsr=0x126<PERR=0x0,LVL=0x1,AT=0x1,FT=0x1,FAV,OW>
data fault: pc=0xf024a128 addr=0x1d4 
sfsr=0x126<PERR=0x0,LVL=0x1,AT=0x1,FT=0x1,FAV,OW>
data fault: pc=0xf024a128 addr=0x1d4 
sfsr=0x126<PERR=0x0,LVL=0x1,AT=0x1,FT=0x1,FAV,OW>
 :