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Re: MP kernel doesn't boot



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Hello,

On May 2, 2008, at 15:21, Michael-John Turner wrote:
On Fri, May 02, 2008 at 12:54:44PM -0400, Michael Lorenz wrote:
Well, the SM50 lacks a cache controller and thus doesn't have any cache coherency support. The question should be why did it work in 2.0 in the
first place.

Interesting - I didn't realise that. I ran a system with a pair of SM50s
and it was rock solid with 2.0 with an SMP kernel.

The CPU has tiny L1 caches, gcc3 probably generated code that thrashed the caches enough to avoid coherency issues by accident.

have fun
Michael
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