Subject: Re: Installing Ross hypersparcs in a SS10
To: Gary Parker <G.J.Parker@lboro.ac.uk>
From: Brett Lymn <blymn@baesystems.com.au>
List: port-sparc
Date: 09/02/2004 08:16:44 
On Wed, Sep 01, 2004 at 03:06:10PM +0100, Gary Parker wrote:
> 
> cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
> 

This means your cpu(s) have cache.

-- 
Brett Lymn