Subject: Re: SS20/MP Watchdog Reset
To: Paul Kranenburg <pk@cs.few.eur.nl>
From: Juergen Hannken-Illjes <hannken@eis.cs.tu-bs.de>
List: port-sparc
Date: 06/17/2004 15:27:44
On Thu, Jun 17, 2004 at 03:16:07PM +0200, Paul Kranenburg wrote:
> > Watchdog resets are caused by taking a trap when traps are disabled.
> > 
> > This particular fault is a level 15 interrupt.  I think the only
> > cause of level 15 interrupts are asynchronous memory errors.
> > Since traps should only be disabled inside trap handlers, you
> > are probably suffering from bad RAM.
> 
> A level 15 interrupt is also sent to all modules if one them resets,
> whatever the reason.
> 
> With some luck, you might still get a stack trace of the reset CPU
> by doing
> 
> 	ok <n> switch-cpu
> 	ok ctrace

Sorry, I replaced the top CPU and reorganized the ram. The machine runs
without problems.
Could this error be the result of an overflowed kernel stack?
-- 
Juergen Hannken-Illjes - hannken@eis.cs.tu-bs.de - TU Braunschweig (Germany)