Subject: Re: CVS commit: src/sys/arch/sparc/sparc
To: Steve Rumble <email@example.com>
From: Paul Kranenburg <firstname.lastname@example.org>
Date: 04/18/2004 02:00:40
> > > My SS20 dual hypersparc 180/150 died building userland with make
> > > -j 4. I was able to serial break into the prom, but upon resuming
> > > it locked hard and refuses to respond to further breaks.
> > 180 & 200MHz parts only run half-speed L2 caches according to
> > mbus.sunhelp.org/modules/index.htm#hyper whereas anything <= 166MHz is
> > full-speed. No idea if that sort've thing would make any difference.
> I wasn't aware of this difference, but apparently mrg's sparc is
> using a dual 100 and a 150 module, which run at different bus
> speeds and cache sizes. It may just be that I have a bum module
> (or a heat issue?) Perhaps one day I'll pull the box from my
> friend's rack and see how the 150 fairs on its own.
The odds are that it is a kernel issue, such as a CPU spinning on a
lock at high IPL.
Try a kernel with DDB and/or LOCKDEBUG, which allows you to get stack
traces for CPUs (or at least those which aren't stuck) if you get a
response to a BREAK at least once.