> >Log Message:
   > >Re-enable the HyperSPARC on-board instruction cache on multi-processor machines.
   > 
   > Cool - is this likely to make it into 2.0 ?
   
   Hopefully.  mgr is stress-testing this now.


my ss10 has been running all night.  it seems pretty good to me.  there's
a little too much use of system time in a "make -j4" build, but certainly
it's much faster than previously.  eg, "openssl speed md5" increased about
30% (about what i measured in the drop with icache disabled.)  it's hard
to tell exactly with my multi-mhz cpus, though.  netbsd's processor affinity
for running processes is obviously "pretty good".  generally a long running
process won't switch cpus, so for my ss10, which has cpus like:

	cpu0 at mainbus0: mid 8: RT620/625 @ 150 MHz, on-chip FPU
	cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
	cpu1 at mainbus0: mid 10: RT620/625 @ 100 MHz, on-chip FPU
	cpu1: 256K byte write-back, 64 bytes/line, sw flush: cache enabled
	cpu2 at mainbus0: mid 11: RT620/625 @ 100 MHz, on-chip FPU
	cpu2: 256K byte write-back, 64 bytes/line, sw flush: cache enabled

you get significant variance on eg "openssl speed" runs.


but this box seems mostly stable to me now, modulo a few kernel messages.


.mrg.