Subject: Re: SMP issue on SS20
To: Zach <firstname.lastname@example.org>
From: None <email@example.com>
Date: 09/11/2003 10:17:36
On Thu, Sep 11, 2003 at 01:19:15AM +0000, Zach wrote:
> i'm missing, or is my system... messed up? The only thing that worries me
> is that i'm not using two identical cpus in the machine. One is a SUN
> branded 60mhz with 1mb L2 cache, and the other is a TI branded 50mhz with
> an L2 cache. I'm assuming that this disparity is the heart of the problem.
> What steps do I take from here to get cpu0 and cpu1 to share the load (like
> they should be doing)?
It could be. As far as I know if you mix CPU modules, they can be different
speeds, but they must have the same cache controller revision (reference
http://mbus.sunhelp.org especially http://mbus.sunhelp.org/misc/genconf.htm).
Under Solaris my sparc 20 has a SM61 and SM71 with the same cache revision
(v3.3 I think). You might want to look at the part numbers on the modules,
reference them with the above site and check the cache controller revision.
Though it doesn't specify, I presume this cache controller issue is OS
independent. Can anyone confirm?