Subject: Re: SMP issue on SS20
To: Christian Smith <csmith@micromuse.com>
From: Zach <md@geekport.com>
List: port-sparc
Date: 09/11/2003 10:35:02
Ahh, that explains why swapping them around solved the problem.  Since 
everybody here seems to have a decent amount of experience with sparc 
hardware, what is the relative performance improvement of going with a pair=
 
of ROSS HyperSPARCs ? I've seen 150mhz's on eBay, and everything i've read 
indicates that they are compatible with the SS20 and NetBSD. Thanks,
=09
=09Zach

On 2003-09-11 at 13:14:01 [+0000], you wrote:
> BTW, make sure the 50MHz modules is in the first mbus slot.
> 
> Cached modules can't talk to the mbus at full speed, so the 50MHz module
> requires a 40MHz mbus. Only the first slot is used when chossing the mbus
> speed, and if the 60MHz module is in that slot, the mbus will be run at
> 50MHz which will be no good for the 50MHz module.
> 
> Then, upgrade to -current as indicated by Brett.
> 
> Christian
> 
> On Thu, 11 Sep 2003, Zach wrote:
> 
> >I bought an SS20 the other day, and decided to put NetBSD on it. The
> >install went fine, so I decided to enable SMP support, since the machine
> >had two processors in it. I built a GENERIC.MP kernel, installed it, and
> >rebooted. When the machine got to the point of enabling the cpu1, it ker=
nel
> >paniced. Not to be disuaded, I moved cpu0 and cpu1 around, and rebooted.
> >The machine booted perfectly into NetBSD 1.6.1 multiuser. My dmesg shows
> >that the machine is indeed enabling cpu1 on boot. However, when I run an=
y
> >programs, they only get executed on cpu0, per the information 'top' is
> >giving me. When I generated an sshd key, the process had a wcpu of 99%, =
but
> >the CPU States: line showed my system was 50% idle. Not to be daunted, I
> >launched another ssh-keygen, and it ran only on cpu0. Is there something
> >i'm missing, or is my system... messed up?  The only thing that worries =
me
> >is that i'm not using two identical cpus in the machine. One is a SUN
> >branded 60mhz with 1mb L2 cache, and the other is a TI branded 50mhz wit=
h
> >an L2 cache. I'm assuming that this disparity is the heart of the proble=
m.
> >What steps do I take from here to get cpu0 and cpu1 to share the load (l=
ike
> >they should be doing)?
> >
> >Thanks for your time,
> >
> >   Zach Dykstra
> >