On Mon, Nov 11, 2002 at 10:24:52PM -0600, T. M. Pederson wrote:
> (Just joined the list; haven't seen the whole thread.)
> 
> I've got a pair of IPC's that also exhibit semi-random compiler death.
> If anyone's interested, they're available.

Yes, this problem is reliably reproductible on all machines which have CPU
with the "sw flush" cache, that is IPC, SS1, SS1+.
SS2 and IPX (with the "hw flush" cache) don't have this problem.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
     NetBSD: 23 ans d'experience feront toujours la difference
--