On Thu, 2 May 2002 01:48:27 +0200
Brad Knowles <brad.knowles@skynet.be> wrote:

> At 1:25 AM +0200 2002/05/02, de SAINT LEGER Rodolphe wrote:
> 
> >  qec0 at sbus0 slot 0 offset 0x20000 vector 4 ipl 2: 128K memory
> >  qe0 at qec0 slot 0 offset 0x0 rev 1 address 08:00:20:86:a2:a0
> >  qe1 at qec0 slot 1 offset 0x0 rev 1 address 08:00:20:86:a2:a0
> >  qe2 at qec0 slot 2 offset 0x0 rev 1 address 08:00:20:86:a2:a0
> >  qe at qec0 slot 3 offset 0x0 not configured
> 
> 	Interesting.  Note that it disables qe3, whereas the U1 appears to bomb.
> 
> 	Out of curiosity, can you build a 64-bit kernel (e.g., sparc64) 
> for use on an SS5 (or similar machine), or does it use 32-bit (e.g., 
> "sparc") kernels exclusively?

As far as I know, it's not possible to use 64bit kernels in a sparc based machine, but I may be wrong...
the sparc64 kernels are only for Ultra-sparc based machines.

Rodolphe