In some email I received from Thilo Manske, sie wrote:
> On Tue, Mar 05 2002 at 23:57:52 +1100, matthew green wrote:
> >    
> >    the SM81 with 2MB cache on the other hand, is a different story.  but then
> >    those aren't useable in a sparc10 anyway. :)
> > wouldn't that be SM82?  (i've never heard or seen of them before.)
> I think "SM81-2". (the page http://mbus.sunhelp.org/modules/ says so)
> 
> I guess SM82 would be the name of a double CPU module but read the text the
> two "name game" links on that page link to see how strict Sun's mbus-naming
> conventions were ;-)

No, that'd be an 812.

502 = 50MHz, 0MB 2nd level cache, 2 CPUs (1 board)
512 = 50MHz, 1MB 2nd level cache, 2 CPUs (1 board)
(http://mbus.sunhelp.org/misc/game52.htm)
61 = 60MHz, 1MB 2nd level cache, 1 CPU
71 = 75MHz, 1MB 2nd level cache, 1 CPU
81 = 85MHz, 1 or 2MB 2nd level cache, 1 CPU

There are no 6*2, 7*2 or 8*2 boards.

http://www.cpe.ku.ac.th/~yuen/204323/sun/SuperSPARC/performance.html

Darren