> |> The 8530 is a fairly dumb chip;

It also has a fairly interesting hw interface just to catch out the unwary:
- the cycle recovery time is quite long (esp. on the original part)
- it latches write data on the LEADING edge of the write pulse

> |> it demands service at least every
> |> couple of characters on input, or input gets dropped.
> 
> but I thought that a real OS would use DMA for high speed serial
> links anyway - configure "RxINT on first character", and have the
> interrupt handler enable the DMA controller.

You can't do it that way - you lose the first character...
I guess you could keep the DMA enabled and take interrupts
from the DMA controller...

> AFAIR the technical manual for the Z80 family always shows SIOs
> in conjunction with DMAs.

I mainly done hdlc with the SCC - you have about 3 bytes times (even
with dma) to service the 'end of frame' interrupt in order to
succesfully receive back to back frames.
My last attempt to use the status FIFO failed because the silicon
was buggy!

I wonder if it would be possibly to get these running at a
reasonable speed (for ppp) by doing data rx and tx within the
trap register window?  (ie just inside the system ISR) you
couldn't do much more that software DMA there, but it
might be enough...

Dunno how you would make it anything other than a hack though?
(still have to watch the interrupt latency, but at least you
would rx most frames)

	David

-- 
David Laight: david@l8s.co.uk