On Sat, Feb 02, 2002 at 07:00:17PM +0000, David Brownlee wrote:
> 	Certainly:
> 
> mainbus0 (root): SUNW,Sun 4/25
> cpu0 at mainbus0: cache chip bug; trap page uncached: W8601/8701 or
> MB86903 @ 33 MHz, on-chip FPU
> cpu0: 64K byte write-through, 32 bytes/line, hw flush: cache enabled

Hum, this is closer to the sparc2 than the 1/1+. So the problem may be 
for all sun4c machines then, not only the ones with the "sw flush" cache.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
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