On Sat, Jan 08, 2000 at 08:47:30AM -0800, Eduardo E. Horvath wrote:

> A Level 15 interrupt is a data access error, or async fault.  
> 
> If you map in the area specified by the `reg' properties of the OBP
> properly and still get async faults, either you are mapping cacheable
> areas as un-cacheable (or visa-versa) or you are mis-interpreting the
> register map.  Try toggling the cacheable attributes.

Setting the BUS_SPACE_MAP_CACHEABLE, too, did not change
anything... But (as Tim proposed) I have used .attributes
on the DBRI node of the OBP:

There is a "pwr-on-auxio" set to 1. Could it be that the
DBRI chip is not yet powered on? Has anyone information
on auxio? (auxio is at obio)

    Ingolf
-- 

Ingolf Koch                      Beste Kneipe in Jena-Ost
PGP: 0x7B3B5661  213C 828E 0C92 16B5  05D0 4D5B A324 EC04