> SInce the SPARC runs at a far higher clock than the Z80 it should be
> able to handle a much higher interrupt frequency

That doesn't necessarily follow - the clock rate is much higher, true,
but the SPARC also has a lot more state to save when an interrupt
occurs (especially if the windows happen to all be full and it has to
spill the trap window to the interrupt stack before it can do
*anything*).  For that matter, the way the 8530 driver is structured,
each interrupt will occupy at least some three or four windows; if you
really need speed, you might want to see if you can recode it (in
assembly, perforce) such that it runs entirely in the trap window.

It seems to me that latency, the delay from the time the chip asks for
the interrupt to the time zstty_rxint() starts reading characters, is
critical - and at present probably rather high.  Short of gross level
violations like recoding the hard handler in assembler so it runs in
the trap window, I'm not sure what to do about this, though....

					der Mouse

			       mouse@rodents.montreal.qc.ca
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