[ repeated to alias due to possible general interest ]

>
>>Actually, the chip wasn't done by NCR, and they know dick about it.
>
>It uses the same core as the NCR5390, which in some versions has
>an identical hardware bug.

Yes, it was actually NCR who funded the effort for the MAC100 (original
name).

>
>Our `SCSI guy' swears that the reselect byte will always be the
>first thing you read out of the FIFO.  The target's LUN/TRN message
>byte is no doubt mixed in later, but it is believable that the
>reselect byte always goes into FIFO slot 0, given that the `clearcmds
>condition' is actually produced by reselection.  The hardware could
>easily shove the reselect byte in ahead of everything else at the
>same time as it stops flushing the FIFO.  Of course, it is also
>believable that they goofed this up too, i.e., that the reselect
>byte competes with incoming command or message bytes, and can
>sometimes lose this race.

--------------------------------
	Emulex Chip Application Notes
	Product:ESP-100
	June 9, 1989
	Number 030-A

	Enable Select/Reselect Non-DMA mode Problem

When the ESP-100 is operating in non-DMA mode, certain system conditions
may prevent the ESP-100 FIFO Register from properly receiving the SCSI bus
ID from the DATA Bus.

The problem occurs if the the ESP-100 has been enabled for Select/Reselect
with parity enabled, and a Select/Reselect occurs while the microprocessor
is accessing the FIFO to set up a non-DMA SELECT or RESELECT command. Two
firmware [ Hah! ] solutions are suggested below:

	* Always issue the SELECT or RESELECT command with DMA

	* Follow the sequence below when loading the FIFO:

		1) Issue a DISABLE SELECTION/RESELECTION command and
		wait for the command complete interrupt.

		2) Service the interrupt:
			a. If the "selected" or "reselected" bit is set in
			the Interrupt Register (bits 0,2, addr 05h), then
			service that event.

			b. Otherwise, verify the "Function Complete" bit is
			set (bit 3 of the Interrupt Register, addr 05h) and
			continue to step 3.

		3) Load the FIFO with the command and/or message bytes.

		4) Issue the ENABLE SELECT/RESELECT command.

		5) Issue the SELECT or RESELECT command.

		NOTE: The microprocessor must complete steps 2 through 4
		within a SCSI select/reselect timeout delay (recommended
		period = 250 ms) minus 20 clock cycles.

------------------------------------

The FIFO in question is the DATA fifo- 16 bytes. The clrcmds condition
refers to the dual ranked command register (2 byte command fifo).

When the ESP acting as an initiator is reselected whils you're manually
loading bytes at the other end of the DATA fifo, the ESP is presented
with two bus masters going through two separate bus arbiters both loading 
the same FIFO- I'd be very surprised if any chip could know what the hell
has happened to which byte in this case without intermediate buffer logic
for both sides. 

When the ESP is using DMA to load the FIFO, it's in control of loading
the FIFO and so can figure out whether it still actually owns the FIFO
prior to loading a byte.

At any rate, if you look at the above two workarounds and agree with
my reasoning in the last two paragraphs you can see why using DMA for
selection commands is something I'd prefer- even if it is *such* a PITA
to do DMA for 6 command bytes + message byte...

-matt