Subject: Re: sun4m sparc processor support status
To: Erik E. Fair <fair@clock.org>
From: Andrew Gillham <gillhaa@ghost.whirlpool.com>
List: port-sparc
Date: 09/15/1997 20:07:24
Erik Fair <fair@clock.org> wrote:
> Here's my impression of where we are:
> 
> MicroSPARC, all models, done & working.
> 
> SuperSPARC Mbus modules with SuperCACHE, done & working.
> 
> SuperSPARC Mbus modules withOUT SuperCACHE, NOT working.

I believe at least one of these is working.  I have the following:
mainbus0 (root): SUNW,SPARCstation-10
cpu0 at mainbus0: TMS390Z50 v1 @ 36 MHz, on-chip FPU
cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l) cache enabled

This is a Sparc 10 model 30, which has no level 2 cache.

-Andrew
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