Here's my impression of where we are:

MicroSPARC, all models, done & working.

SuperSPARC Mbus modules with SuperCACHE, done & working.

SuperSPARC Mbus modules withOUT SuperCACHE, NOT working.

HyperSPARC Mbus modules, recognized, but NOT working.

Multiprocessor Mbus modules recognized, and working, but only on one
processor (others are recognized and shut off).

	comments or additions?

	Erik <fair@clock.org>