Subject: Re: HyperSPARC
To: Brian Baird <email@example.com>
From: Paul Kranenburg <firstname.lastname@example.org>
Date: 08/27/1997 23:19:50
> At least some of those changes came from me, although my version is
> marginally different in some messages. I have a sparc 10 with dual
> RT625 hypersparcs. With what's there a kernel will boot and recognise
> devices. In order to have the le ethernet work, you need to disable
> sc->sc_hasiocache in iommu.c.
In order to take full advantage of cache-coherent DVMA, the routines that
load the IOMMU page tables should changed to allocate DVMA addresses
that are congruent to kernel virtual addresses mapping the same physical
I was looking at the extent_*() routines to assist with this, but it
doesn't seem to directly support this type of resource allocation.
> In order to even get through the boot
> code you need to turn off the cpu's instruction buffer from the prom:
> ok reset
> ok ross625
> ok ibuf-off
> ok boot netbsd -s
I hope not having to litter the boot-blocks with knowledge of specific
cache implementations floating around..
Maybe it is sufficient to link the first and second stage boot programs
at different virtual addresses to avoid aliasing across the I- and D-cache.