So, after all of that work Paul did on the SPARC cache code, I decided
to try it out on the SS10 in my lab...

So, it didn't get nearly as far as it used to ... I saw:

    bootstrap: PROM has invalid mapping for system interrupt register

So, I check the /interrupt node in the prom, and see that I should
be getting:

	ffee6000 ffee5000 ffee4000 ffee3000 ffee2000

romprop() is indeed getting these values, and the new mapping for the
first one is installed... I added some printfs to the code, and see
that ra.ra_nvaddrs == 5 before the first iteration of the loop,
but immediately after the setpte4m() call, ra.ra_nvaddrs == 0!!

Then, since it falls out of the loop, i is now equal to 1, but
ra.ra_vaddrs[1] == 0x0!!

So, something in setpte4m() is trashing the memory that the romaux
is in ... odd, since the romaux is an automatic...

Any ideas?

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                               Home: 408.866.1912
NAS: M/S 258-6                                          Work: 415.604.0935
Moffett Field, CA 94035                                Pager: 415.428.6939