>What function is then served by the code in cache_enable?

It messes up booting on a non-Ecache SS20. :-)

(I started with Aaron's NetBSD code when porting BSD/OS to the
sun4m, and spent at least a day on this problem alone, poking
through memory to see where the data went -- I thought the problem
was in my register window handler.)

>Research ...

Ah.  In that case, feel free to write the code to push dirty cache
lines...

On E-cache machines, the D-cache is set up as write-through so that
the Ecache can (as the manual puts it) `maintain the inclusion
property'.  This may (or may not) mean that you have to turn off
the I&D caches first (but since the Icache is never written, and
the Dcache is write-through, this is easy on Ecache systems).

To flush dirty lines from the Ecache, use the MXCC stream data
registers to copy the dirty subblocks `to themselves' -- the read
will issue a Coherent Read cycle (getting the data from the cache
on the VBus) and the write a C-W-Invalidate, so that the cache data
will be sent to main memory on the MBus, and the Own bit on that
subblock should get turned off.  You will probably just want to
iterate through the entire Ecache one block at a time, looking
for O-bits in the cache tags, and when found, constructing the
corresponding physical address from the rest of the cache tag and
the offset.

Chris