Chris Torek wrote:
>
> [supersparc coherency problems]

Very interesting. Good detective work! So, if I understand this correctly,
then a stopgap measure to fix this problem is to just make sure that page-
zero and page-copy are done with caching enabled. A diff to implement this
on the supersparc is attached below; it applies to rev. 1.67 of pmap.c.
Could someone who has this problem (I've never seen it myself) try this
patch and let me know what happens?

> (There are still some other bugs remaining once you fix that, but
> those are pretty minor.  The big ugliness is that you need to flush
> any Ecache contents for the pages that map the iopte's in the iommu,
> but typically there is nothing there to flush, so the missing code
> here does not hurt you.  There are also some issues with getting
> reliable M and R bits, as described in section 8.5.3 of the big
> manual Aaron has.)

So right now the iommu init code uncaches the target area before writing
the new pagetables into it. Since the iommu bypasses the caches, this should
work fine since it only sees what's in memory, and the CPU has written 
directly into memory. If there's junk in the cache, it should never get
seen by anything, since (as far as I remember) the CPU never really needs
to read or process the iopte tables.

In any case, this problem would be fixed if I could just scrape up enough
time to write (or integrate) and debug an ecache-flush routine. :-/

-Aaron

Index: pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc/sparc/pmap.c,v
retrieving revision 1.67
diff -c -r1.67 pmap.c
*** pmap.c	1996/11/09 23:08:56	1.67
--- pmap.c	1997/02/17 15:35:40
***************
*** 6185,6192 ****
  		if (vactype != VAC_NONE)
  			pv_flushcache(pvhead(pa));
  	}
! 	pte = ~SRMMU_PG_C & (SRMMU_TEPTE | PPROT_S | PPROT_WRITE |
! 	      (atop(pa) << SRMMU_PPNSHIFT));
  	va = vpage[0];
  	setpte4m((vm_offset_t) va, pte);
  	qzero(va, NBPG);
--- 6185,6197 ----
  		if (vactype != VAC_NONE)
  			pv_flushcache(pvhead(pa));
  	}
! 	pte = (SRMMU_TEPTE | PPROT_S | PPROT_WRITE |
! 	       (atop(pa) << SRMMU_PPNSHIFT));
! 	if (mmumod == SUN4M_MMU_SS)
! 		pte |= SRMMU_PG_C;
! 	else
! 		pte &= ~SRMMU_PG_C;
! 
  	va = vpage[0];
  	setpte4m((vm_offset_t) va, pte);
  	qzero(va, NBPG);
***************
*** 6221,6228 ****
  		if (vactype != VAC_NONE)
  			pv_flushcache(pvhead(dst));
  	}
! 	dpte = ~SRMMU_PG_C & (SRMMU_TEPTE | PPROT_S | PPROT_WRITE |
! 		(atop(dst) << SRMMU_PPNSHIFT));
  
  	sva = vpage[0];
  	dva = vpage[1];
--- 6226,6237 ----
  		if (vactype != VAC_NONE)
  			pv_flushcache(pvhead(dst));
  	}
! 	dpte = (SRMMU_TEPTE | PPROT_S | PPROT_WRITE |
! 	       (atop(dst) << SRMMU_PPNSHIFT));
! 	if (mmumod == SUN4M_MMU_SS)
! 		dpte |= SRMMU_PG_C;
! 	else
! 		dpte &= ~SRMMU_PG_C;
  
  	sva = vpage[0];
  	dva = vpage[1];